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XCR3256XL-10FTG256I PDF预览

XCR3256XL-10FTG256I

更新时间: 2024-11-13 15:58:23
品牌 Logo 应用领域
赛灵思 - XILINX 时钟输入元件可编程逻辑
页数 文件大小 规格书
13页 220K
描述
EE PLD, 10ns, 256-Cell, CMOS, PBGA256, FBGA-256

XCR3256XL-10FTG256I 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA, BGA256,16X16,40针数:256
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:12 weeks
风险等级:5.11Is Samacsys:N
其他特性:YES最大时钟频率:105 MHz
系统内可编程:YESJESD-30 代码:S-PBGA-B256
JESD-609代码:e1JTAG BST:YES
长度:17 mm湿度敏感等级:3
专用输入次数:I/O 线路数量:164
宏单元数:256端子数量:256
最高工作温度:85 °C最低工作温度:-40 °C
组织:0 DEDICATED INPUTS, 164 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA256,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):260
电源:3/3.3 V可编程逻辑类型:EE PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:1.55 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:2.7 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

XCR3256XL-10FTG256I 数据手册

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0
R
XCR3256XL 256 Macrocell CPLD  
0
14  
DS013 (v2.7) March 31, 2006  
Product Specification  
Features  
Description  
Low power 3.3V 256 macrocell CPLD  
The CoolRunner™ XPLA3 XCR3256XL device is a 3.3V,  
256 macrocell CPLD targeted at power sensitive designs  
that require leading edge programmable logic solutions. A  
total of 16 function blocks provide 6,000 usable gates.  
Pin-to-pin propagation delays are as fast as 7.0 ns with a  
maximum system frequency of 154 MHz.  
7.0 ns pin-to-pin logic delays  
System frequencies up to 154 MHz  
256 macrocells with 6,000 usable gates  
Available in small footprint packages  
-
-
-
-
144-pin TQFP (120 user I/O pins)  
208-pin PQFP (164 user I/O)  
256-ball FBGA (164 user I/O)  
280-ball CS BGA (164 user I/O)  
TotalCMOS Design Technique for Fast  
Zero Power  
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,  
both in process technology and design technique. These  
CPLDs employ a cascade of CMOS gates to implement  
their sum of products, instead of the traditional sense amp  
approach. This CMOS gate implementation allows Xilinx  
CPLDs to offer devices that are both high performance and  
low power, breaking the paradigm that to have low power,  
you must have low performance. Refer to Figure 1 and  
Table 1 showing the ICC vs. Frequency of our XCR3256XL  
TotalCMOS CPLD (data taken with 16 resetable up/down,  
16-bit counters at 3.3V, 25°C).  
Optimized for 3.3V systems  
-
-
-
-
Ultra low power operation  
Typical Standby Current of 18 μA at 25°C  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
Fast Zero Power™ (FZP) CMOS design  
technology  
3.3V PCI electrical specification compatible outputs  
(no internal clamp diode on any input or I/O)  
-
-
Advanced system features  
140  
120  
100  
80  
-
-
-
-
-
-
-
-
In-system programming  
Input registers  
Predictable timing model  
Up to 23 clocks available per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
Eight product term control terms per function block  
60  
40  
Fast ISP programming times  
Port Enable pin for additional I/O  
2.7V to 3.6V supply voltage at industrial grade voltage  
range  
20  
0
Programmable slew rate control per output  
Security bit prevents unauthorized access  
20  
0
XCR3256XL  
40  
60  
80  
100  
120  
140  
160  
Refer to the CoolRunner™ XPLA3 family data sheet  
Frequency (MHz)  
(DS012) for architecture description  
Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C  
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C  
Frequency (MHz)  
0
1
10  
20  
40  
60  
80  
100  
120  
140  
Typical ICC (mA)  
0.018  
0.98  
9.69  
19.3  
38.1  
56.2  
73.7  
90.8  
107.3  
123.9  
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS013 (v2.7) March 31, 2006  
 
 

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