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XCR3256XL-10PQG208C

更新时间： 2024-09-25 15:58:23
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R
XCR3256XL 256 Macrocell CPLD  
0
14  
DS013 (v2.7) March 31, 2006  
Product Specification  
Features  
Description  
•
•
•
•
•
Low power 3.3V 256 macrocell CPLD  
The CoolRunner™ XPLA3 XCR3256XL device is a 3.3V,  
256 macrocell CPLD targeted at power sensitive designs  
that require leading edge programmable logic solutions. A  
total of 16 function blocks provide 6,000 usable gates.  
Pin-to-pin propagation delays are as fast as 7.0 ns with a  
maximum system frequency of 154 MHz.  
7.0 ns pin-to-pin logic delays  
System frequencies up to 154 MHz  
256 macrocells with 6,000 usable gates  
Available in small footprint packages  
-
-
-
-
144-pin TQFP (120 user I/O pins)  
208-pin PQFP (164 user I/O)  
256-ball FBGA (164 user I/O)  
280-ball CS BGA (164 user I/O)  
TotalCMOS Design Technique for Fast  
Zero Power  
CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution,  
both in process technology and design technique. These  
CPLDs employ a cascade of CMOS gates to implement  
their sum of products, instead of the traditional sense amp  
approach. This CMOS gate implementation allows Xilinx  
CPLDs to offer devices that are both high performance and  
low power, breaking the paradigm that to have low power,  
you must have low performance. Refer to Figure 1 and  
Table 1 showing the ICC vs. Frequency of our XCR3256XL  
TotalCMOS CPLD (data taken with 16 resetable up/down,  
16-bit counters at 3.3V, 25°C).  
•
Optimized for 3.3V systems  
-
-
-
-
Ultra low power operation  
Typical Standby Current of 18 μA at 25°C  
5V tolerant I/O pins with 3.3V core supply  
Advanced 0.35 micron five layer metal EEPROM  
process  
Fast Zero Power™ (FZP) CMOS design  
technology  
3.3V PCI electrical specification compatible outputs  
(no internal clamp diode on any input or I/O)  
-
-
•
Advanced system features  
140  
120  
100  
80  
-
-
-
-
-
-
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In-system programming  
Input registers  
Predictable timing model  
Up to 23 clocks available per function block  
Excellent pin retention during design changes  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Four global clocks  
Eight product term control terms per function block  
60  
40  
•
•
•
Fast ISP programming times  
Port Enable pin for additional I/O  
2.7V to 3.6V supply voltage at industrial grade voltage  
range  
20  
0
•
•
•
Programmable slew rate control per output  
Security bit prevents unauthorized access  
20  
0
XCR3256XL  
40  
60  
80  
100  
120  
140  
160  
Refer to the CoolRunner™ XPLA3 family data sheet  
Frequency (MHz)  
(DS012) for architecture description  
Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C  
Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C  
Frequency (MHz)  
0
1
10  
20  
40  
60  
80  
100  
120  
140  
Typical ICC (mA)  
0.018  
0.98  
9.69  
19.3  
38.1  
56.2  
73.7  
90.8  
107.3  
123.9  
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS013 (v2.7) March 31, 2006  
 
 
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XCR3256XL-10PQG208C 替代型号

型号 品牌 替代类型 描述 数据表
XCR3256XL-7PQ208C XILINX

完全替代

 256 Macrocell CPLD
XCR3256XL-10PQ208C XILINX

完全替代

 256 Macrocell CPLD

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 		EE PLD, 10ns, 256-Cell, CMOS, PQFP208, LEAD FREE, PLASTIC, QFP-208
XCR3256XL-10TQ144C XILINX

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 		256 Macrocell CPLD
XCR3256XL-10TQ144I XILINX

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XCR3256XL-10TQG144C XILINX

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XCR3256XL-10TQG144I XILINX

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 		EE PLD, 10ns, 256-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144
XCR3256XL-12CS280C XILINX

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 		256 Macrocell CPLD
XCR3256XL-12CS280I XILINX

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 		256 Macrocell CPLD
XCR3256XL-12FT256C XILINX

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 		256 Macrocell CPLD
XCR3256XL-12FT256I XILINX

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 		256 Macrocell CPLD
XCR3256XL-12FTG256I XILINX

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 		EE PLD, 12ns, 256-Cell, CMOS, PBGA256, FBGA-256

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