Datasheet > XCR3256XL-7.5CS280I

XCR3256XL-7.5CS280I

更新时间： 2024-09-26 07:10:27

品牌	Logo	应用领域
赛灵思 - XILINX		时钟可编程逻辑
页数	文件大小	规格书
11页	140K
描述
EE PLD, 7.5ns, CMOS, PBGA280, CHIP SCALE, BGA-280

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XCR3256XL-7.5CS280I 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	TFBGA,	针数：	280
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.17	最大时钟频率：	167 MHz
JESD-30 代码：	S-PBGA-B280	JESD-609代码：	e0
长度：	16 mm	湿度敏感等级：	3
I/O 线路数量：	160	端子数量：	280
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	160 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	240	可编程逻辑类型：	EE PLD
传播延迟：	7.5 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压：	3.6 V
最小供电电压：	2.7 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	16 mm

XCR3256XL-7.5CS280I 数据手册

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APPLICATION NOTE

CoolRunner™ XPLA3 CPLD

14*

DS012 (v1.1) March 3, 2000

Advance Product Specification

Features

Family Overview

•

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

Innovative XPLA3 architecture combines high speed

with extreme flexibility

Based on industry's first TotalCMOS™ PLD - both

CMOS design and process technologies

Advanced 0.35µ five metal layer E²CMOS process

The CoolRunner XPLA3 (eXtended Programmable Logic

Array) family of CPLDs is targeted for low power systems

that include portable, handheld, and power sensitive appli-

cations. Each member of the XPLA3 family includes Fast

Zero Power (FZP) design technology that combines low

power and high speed. With this design technique, the

XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while

simultaneously delivering power that is less than 100 µA at

standby without the need for "turbo bits" or other power

down schemes. By replacing conventional sense amplifier

methods for implementing product terms (a technique that

has been used in PLDs since the bipolar era) with a cas-

caded chain of pure CMOS gates, the dynamic power is

also substantially lower than any competing CPLD. Cool-

Runner devices are the only TotalCMOS PLDs, as they use

both a CMOS process technology and the patented full

CMOS FZP design technique.

•

1,000 erase/program cycles guaranteed

20 years data retention guaranteed

3V, In-System Programmable (ISP) using JTAG IEEE

1149.1 interface

Full Boundary Scan Test (IEEE 1149.1)

•

Ultra-low static power of less than 100 µA

Simple deterministic timing model

Support for complex asynchronous clocking

16 product term clocks and four local control term

clocks per logic block

Four global clocks and one universal control term

clock per device

To the original XPLA architecture, XPLA3 adds a direct

input register path, multiple clocks (both dedicated and

product term generated), and both reset and preset for

each macrocell, with a full PLA structure. These enhance-

ments deliver high speed coupled with very flexible logic

allocation which results in the ability to make design

changes without changing pinout. The XPLA3 logic block

includes a pool of 48 product terms that can be allocated to

any macrocell in the logic block. Logic that is common to

multiple macrocells can be placed on a single PLA product

term and shared, effectively increasing design density.

•

Excellent pin retention during design changes

5V tolerant I/O pins

Input register set up time of 1.7 ns

Logic expandable to 48 product terms

High-speed pin-to-pin delays of 5.0 ns

Slew rate control per macrocell

100% routable

Security bit prevents unauthorized access

Supports hot-plugging capability

Design entry/verification using Xilinx or industry

standard CAE tools

XPLA3 CPLDs are supported by WebPACK from Xilinx and

industry standard CAE tools (Cadence/OrCAD, Exemplar

Logic, Mentor, Synopsys, Viewlogic, andd Synplicity), using

text (ABEL, VHDL, Verilog) and schematic capture design

entry. Design verification uses industry standard simulators

for functional and timing simulation. Development is sup-

ported on personal computer, Sparc, and HP platforms.

Device fitting uses Xilinx developed tools including

WebFITTER.

•

Innovative Control Term structure provides:

Asynchronous macrocell clocking

Asynchronous macrocell register preset/reset

Clock enable control per macrocell

•

Four output enable controls per logic block

Foldback NAND for synthesis optimization

Global 3-state which facilitates "bed of nails" testing

Available in Chip-scale BGA, and QFP packages

Commercial and extended voltage industrial grades

Pin compatible with existing CoolRunner low-power

family devices

The XPLA3 family features also include industry-standard,

IEEE 1149.1, JTAG interface through which In-System Pro-

gramming (ISP) and reprogramming of the device can

DS012 (v1.1) March 3, 2000

www.xilinx.com

1-800-255-7778

12 3 4 5 6 7...11

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与XCR3256XL-7.5CS280I相关器件

型号	品牌	获取价格	描述	数据表
XCR3256XL-7.5CSG280I	XILINX	获取价格	EE PLD, 7.5ns, CMOS, PBGA280, CHIP SCALE, BGA-280
XCR3256XL-7.5PQ208C	XILINX	获取价格	EE PLD, 7.5ns, CMOS, PQFP208, QFP-208
XCR3256XL-7.5TQ144I	XILINX	获取价格	EE PLD, 7.5ns, CMOS, PQFP144, QFP-144
XCR3256XL-7.5TQG144C	XILINX	获取价格	EE PLD, 7.5ns, CMOS, PQFP144, QFP-144
XCR3256XL-7.5TQG144I	XILINX	获取价格	EE PLD, 7.5ns, CMOS, PQFP144, QFP-144
XCR3256XL-7CS280C	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7CS280I	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7FT256C	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7FT256I	XILINX	获取价格	256 Macrocell CPLD
XCR3256XL-7FTG256C	XILINX	获取价格	EE PLD, 7.5ns, 256-Cell, CMOS, PBGA256, FBGA-256

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