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XCF04SVO20C PDF预览

XCF04SVO20C

更新时间: 2024-02-27 03:29:24
品牌 Logo 应用领域
赛灵思 - XILINX 可编程只读存储器
页数 文件大小 规格书
46页 579K
描述
Platform Flash In-System Programmable Configuration PROMS

XCF04SVO20C 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.43
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5024 mm内存密度:4194304 bit
内存集成电路类型:CONFIGURATION MEMORY内存宽度:1
湿度敏感等级:3功能数量:1
端子数量:20字数:4194304 words
字数代码:4000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4MX1封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行:SERIAL
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:1.19 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

XCF04SVO20C 数据手册

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<BL Blue>  
Platform Flash In-System  
Programmable Configuration  
PROMS  
R
0
DS123 (v2.9) May 09, 2006  
Product Specification  
Features  
In-System Programmable PROMs for Configuration of  
Xilinx FPGAs  
XCF01S/XCF02S/XCF04S  
3.3V supply voltage  
Low-Power Advanced CMOS NOR FLASH Process  
Endurance of 20,000 Program/Erase Cycles  
Serial FPGA configuration interface (up to 33 MHz)  
Available in small-footprint VO20 and VOG20  
packages.  
Operation over Full Industrial Temperature Range  
(–40°C to +85°C)  
XCF08P/XCF16P/XCF32P  
IEEE Standard 1149.1/1532 Boundary-Scan (JTAG)  
Support for Programming, Prototyping, and Testing  
1.8V supply voltage  
Serial or parallel FPGA configuration interface  
(up to 33 MHz)  
JTAG Command Initiation of Standard FPGA  
Configuration  
Available in small-footprint VO48, VOG48, FS48,  
and FSG48 packages  
Cascadable for Storing Longer or Multiple Bitstreams  
Dedicated Boundary-Scan (JTAG) I/O Power Supply  
Design revision technology enables storing and  
accessing multiple design revisions for  
configuration  
(V  
)
CCJ  
I/O Pins Compatible with Voltage Levels Ranging From  
1.5V to 3.3V  
Built-in data decompressor compatible with Xilinx  
advanced compression technology  
Design Support Using the Xilinx Alliance ISE and  
Foundation ISE Series Software Packages  
Table 1: Platform Flash PROM Features  
Program  
In-system  
via JTAG  
Serial  
Parallel  
Design  
Density  
VCCINT VCCO Range VCCJ Range  
Packages  
Compression  
Device  
Config. Config. Revisioning  
XCF01S  
XCF02S  
XCF04S  
1 Mbit  
2 Mbit  
4 Mbit  
3.3V 1.8V – 3.3V 2.5V – 3.3V VO20/VOG20  
3.3V 1.8V – 3.3V 2.5V – 3.3V VO20/VOG20  
3.3V 1.8V – 3.3V 2.5V – 3.3V VO20/VOG20  
VO48/VOG48  
1.8V 1.5V – 3.3V 2.5V – 3.3V  
FS48/FSG48  
XCF08P  
8 Mbit  
VO48/VOG48  
1.8V 1.5V – 3.3V 2.5V – 3.3V  
FS48/FSG48  
XCF16P 16 Mbit  
XCF32P 32 Mbit  
VO48/VOG48  
1.8V 1.5V – 3.3V 2.5V – 3.3V  
FS48/FSG48  
Description  
Xilinx introduces the Platform Flash series of in-system  
programmable configuration PROMs. Available in 1 to 32  
Megabit (Mbit) densities, these PROMs provide an  
easy-to-use, cost-effective, and reprogrammable method  
for storing large Xilinx FPGA configuration bitstreams. The  
Platform Flash PROM series includes both the 3.3V  
XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS  
version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that  
support Master Serial and Slave Serial FPGA configuration  
modes (Figure 1, page 2). The XCFxxP version includes  
32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master  
Serial, Slave Serial, Master SelectMAP, and Slave  
SelectMAP FPGA configuration modes (Figure 2, page 2).  
A summary of the Platform Flash PROM family members  
and supported features is shown in Table 1.  
© 2003-2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS123 (v2.9) May 09, 2006  
www.xilinx.com  
1

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