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XC4005-5PC84C PDF预览

XC4005-5PC84C

更新时间: 2024-09-20 20:26:31
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
40页 350K
描述
Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, PQCC84, PLASTIC, LCC-84

XC4005-5PC84C 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-84
针数:84Reach Compliance Code:unknown
ECCN代码:3A991HTS代码:8542.39.00.01
风险等级:5.78Is Samacsys:N
其他特性:616 FLIP-FLOPS; TYP. GATES = 4000-5000最大时钟频率:133.3 MHz
CLB-Max的组合延迟:4.5 nsJESD-30 代码:S-PQCC-J84
JESD-609代码:e0长度:29.3116 mm
湿度敏感等级:3可配置逻辑块数量:196
等效关口数量:4000输入次数:112
逻辑单元数量:196输出次数:112
端子数量:84最高工作温度:85 °C
最低工作温度:组织:196 CLBS, 4000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Field Programmable Gate Arrays
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn85Pb15)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:29.3116 mmBase Number Matches:1

XC4005-5PC84C 数据手册

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XC4000, XC4000A, XC4000H  
Logic Cell Array Families  
Product Description  
Description  
Features  
The XC4000 families of Field-Programmable Gate Arrays  
(FPGAs) provide the benefits of custom CMOS VLSI, while  
avoiding the initial cost, time delay, and inherent risk of a  
conventional masked gate array.  
Third Generation Field-Programmable Gate Arrays  
– Abundant flip-flops  
– Flexible function generators  
– On-chip ultra-fast RAM  
– Dedicated high-speed carry-propagation circuit  
– Wide edge decoders  
– Hierarchy of interconnect lines  
– Internal 3-state bus capability  
– Eight global low-skew clock or signal distribution  
network  
The XC4000 families provide a regular, flexible, program-  
mable architecture of Configurable Logic Blocks (CLBs),  
interconnected by a powerful hierarchy of versatile routing  
resources, and surrounded by a perimeter of program-  
mable Input/Output Blocks (IOBs).  
XC4000-familydeviceshavegenerousroutingresourcesto  
accommodate the most complex interconnect patterns.  
XC4000A devices have reduced sets of routing resources,  
sufficient for their smaller size. XC4000H high I/O devices  
maintain the same routing resources and CLB structure as  
the XC4000 family, while nearly doubling the available I/O.  
Flexible Array Architecture  
– Programmable logic blocks and I/O blocks  
– Programmable interconnects and wide decoders  
Sub-micron CMOS Process  
– High-speed logic and Interconnect  
– Low power consumption  
The devices are customized by loading configuration data  
intotheinternalmemorycells.TheFPGAcaneitheractively  
read its configuration data out of external serial or byte-  
parallel PROM (master modes), or the configuration data  
can be written into the FPGA (slave and peripheral modes).  
Systems-Oriented Features  
– IEEE 1149.1-compatible boundary-scan logic support  
– Programmable output slew rate  
– Programmable input pull-up or pull-down resistors  
– 12-mA sink current per output (XC4000 family)  
– 24-mA sink current per output (XC4000A and  
XC4000H families)  
The XC4000 families are supported by powerful and so-  
phisticated software, covering every aspect of design: from  
schematic entry, to simulation, to automatic block place-  
ment and routing of interconnects, and finally the creation  
of the configuration bit stream.  
Configured by Loading Binary File  
– Unlimited reprogrammability  
– Six programming modes  
Since Xilinx FPGAs can be reprogrammed an unlimited  
number of times, they can be used in innovative designs  
where hardware is changed dynamically, or where hard-  
waremustbeadaptedtodifferentuserapplications.FPGAs  
are ideal for shortening the design and development cycle,  
but they also offer a cost-effective solution for production  
rates well beyond 1000 systems per month.  
XACT Development System runs on ’386/’486-type PC,  
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700  
series  
– Interfaces to popular design environments like  
Viewlogic, Mentor Graphics and OrCAD  
– Fully automatic partitioning, placement and routing  
– Interactive design editor for design optimization  
– 288 macros, 34 hard macros, RAM/ROM compiler  
Table 1. The XC4000 Families of Field-Programmable Gate Arrays  
Device  
XC4002A 4003/3A 4003H 4004A 4005/5A 4005H 4006  
4008 4010/10D 4013/13D 4020  
4025  
Appr. Gate Count  
CLB Matrix  
Number of CLBs  
Number of Flip-Flops  
2,000  
8 x 8  
64  
256  
24  
3,000  
3,000  
4,000  
5,000  
5,000  
6,000  
8,000  
10,000  
13,000 20,000 25,000  
24 x 24 28 x 28 32 x 32  
10 x 10 10 x 10 12 x 12 14 x 14 14 x 14 16 x 16 18 x 18 20 x 20  
100  
360  
30  
100  
200  
30  
144  
480  
36  
196  
616  
42  
196  
392  
42  
256  
768  
48  
324  
936  
54  
400  
1,120  
60  
576  
1,536  
72  
784  
2,016  
84  
1,024  
2,560  
96  
Max Decode Inputs  
(per side)  
Max RAM Bits  
Number of IOBs  
2,048  
64  
3,200  
80  
3,200  
160  
4,608  
96  
6,272  
112  
6,272  
192  
8,192  
128  
10,368 12,800* 18,432* 25,088 32,768  
144 160 192 224 256  
*XC4010D and XC4013D have no RAM  
2-7  

XC4005-5PC84C 替代型号

型号 品牌 替代类型 描述 数据表
XCS10-3PC84C XILINX

类似代替

Spartan and Spartan-XL Families Field Programmable Gate Arrays

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