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XC4005A-5PQ160C

更新时间： 2024-09-19 22:41:19
品牌 Logo 应用领域
赛灵思 - XILINX 现场可编程门阵列可编程逻辑栅时钟
页数 文件大小 规格书
16页 100K
描述
Logic Cell Array Family

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中文翻译

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XC4005A-5PQ160C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, QFP-160
针数：160Reach Compliance Code：not_compliant
ECCN代码：3A991HTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
其他特性：616 FLIP-FLOPS; TYP. GATES = 4000-5000最大时钟频率：133.3 MHz
CLB-Max的组合延迟：4.5 nsJESD-30 代码：S-PQFP-G160
JESD-609代码：e0长度：28 mm
湿度敏感等级：3可配置逻辑块数量：196
等效关口数量：4000输入次数：112
逻辑单元数量：196输出次数：112
端子数量：160最高工作温度：85 °C
最低工作温度：组织：196 CLBS, 4000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP160,1.2SQ封装形状：SQUARE
封装形式：FLATPACK电源：5 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：3.92 mm子类别：Field Programmable Gate Arrays
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
宽度：28 mmBase Number Matches：1

XC4005A-5PQ160C 数据手册

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XC4000A  
Logic Cell Array Family  
Product Specifications  
Description  
Features  
TheXC4000AfamilyofFPGAsoffersfourdevicesatthelow  
end of the XC4000 family complexity range. XC4000A  
differs from XC4000 in four areas: fewer routing resources,  
fewer wide-edge decoders, higher output sink current, and  
improved output slew-rate control.  
•
Third Generation Field-Programmable Gate Arrays  
– Abundant flip-flops  
– Flexible function generators  
– On-chip ultra-fast RAM  
– Dedicated high-speed carry-propagation circuit  
– Wide edge decoders (two per edge)  
– Hierarchy of interconnect lines  
– Internal 3-state bus capability  
– Eight global low-skew clock or signal distribution  
network  
•
The XC4000 routing structure is optimized for smaller  
designs, naturally requiring fewer routing resources. The  
XC4000A devices have four Longlines and four single-  
length lines per row and column, while the XC4000  
devices have six Longlines and eight single-length lines  
per row and column. This results in a smaller chip area  
and lower cost per device.  
•
•
•
Flexible Array Architecture  
– Programmable logic blocks and I/O blocks  
– Programmable interconnects and wide decoders  
•
•
•
XC4000A has two wide-edge decoders on every device  
edge, while the XC4000 has four. All other wide-decoder  
features are identical in XC4000 and XC4000A.  
Sub-micron CMOS Process  
– High-speed logic and Interconnect  
– Low power consumption  
XC4000A outputs are specified at 24 mA, sink current,  
while XC4000 outputs are specified at 12 mA. The source  
current is the same 4 mA for both families.  
Systems-Oriented Features  
– IEEE 1149.1-compatible boundary-scan logic support  
– Programmable output slew rate (4 modes)  
– Programmable input pull-up or pull-down resistors  
– 24-mA sink current per output (48 per pair)  
The XC4000A family offers a more sophisticated output  
slew-rate control structure with four configurable options  
for each individual output driver: fast, medium fast, me-  
dium slow, and slow. Slew-rate control can alleviate  
ground-bounce problems when multiple outputs switch  
simultaneously, and it can reduce or eliminate crosstalk  
and transmission-line effects on printed circuit boards.  
•
•
Configured by Loading Binary File  
– Unlimited reprogrammability  
– Six programming modes  
XACT Development System runs on ’386/’486-type PC,  
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700 Series  
– Interfaces to popular design environments like  
Viewlogic, Mentor Graphics and OrCAD  
– Fully automatic partitioning, placement and routing  
– Interactive design editor for design optimization  
– 288 macros, 34 hard macros, RAM/ROM compiler  
Note that the XC4003 and XC4005 devices are available in  
both flavors, the lower-priced XC4003A/XC4005A with re-  
duced routing, and the higher-priced XC4003/XC4005 with  
more abundant routing resources. The XC4000A devices  
are intended for less demanding and more structured  
designs, and the XC4000 devices for more random designs  
requiring additional routing resources.  
The equivalent devices are pin-compatible and are avail-  
able in identical packages, but they are not bitstream  
compatible. In order to move from a XC4000A to a XC4000,  
or vice versa, the design must be recompiled.  
Table 1. The XC4000A Family of Field-Programmable Gate Arrays  
Device  
Appr. Gate Count  
CLB Matrix  
Number of CLBs  
Number of Flip-Flops  
Max Decode Inputs (per side)  
Max RAM Bits  
XC4002A  
XC4003A  
XC4004A  
XC4005A  
2,000  
8 x 8  
64  
256  
24  
2,048  
64  
3,000  
10 x 10  
100  
360  
30  
3,200  
80  
4,000  
12 x 12  
144  
480  
36  
4,608  
96  
5,000  
14 x 14  
196  
616  
42  
6,272  
112  
Number of IOBs  
2-71  
1234567...16

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XC4005A-5PQ208I XILINX

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XC4005A-5TQ144C XILINX

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 		Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, PQFP144, PL
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 		Field Programmable Gate Array, 196 CLBs, 4000 Gates, 133.3MHz, 196-Cell, CMOS, PQFP144, PL
XC4005A-6PC84C ETC

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XC4005A-6PC84I XILINX

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 		Field Programmable Gate Array, 196 CLBs, 4000 Gates, 90.9MHz, 196-Cell, CMOS, PQCC84, PLAS
XC4005A-6PG156C XILINX

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 		Field Programmable Gate Array, 196 CLBs, 4000 Gates, 90.9MHz, 196-Cell, CMOS, CPGA156, CER
XC4005A-6PG156I XILINX

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 		Field Programmable Gate Array, 196 CLBs, 4000 Gates, 90.9MHz, 196-Cell, CMOS, CPGA156, CER
XC4005A-6PQ160C XILINX

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 		Field Programmable Gate Array, 196 CLBs, 4000 Gates, 90.9MHz, 196-Cell, CMOS, PQFP160, PLA

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