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XC2VP7-7FG456I

更新时间： 2024-11-06 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
268页 1760K
描述
Field Programmable Gate Array, 1232 CLBs, 1350MHz, 11088-Cell, CMOS, PBGA456, 1 MM PITCH, FBGA-456

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XC2VP7-7FG456I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：1 MM PITCH, FBGA-456针数：456
Reach Compliance Code：not_compliant风险等级：5.28
最大时钟频率：1350 MHzCLB-Max的组合延迟：0.28 ns
JESD-30 代码：S-PBGA-B456JESD-609代码：e0
长度：23 mm湿度敏感等级：3
可配置逻辑块数量：1232输入次数：248
逻辑单元数量：11088输出次数：248
端子数量：456组织：1232 CLBS
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA456,22X22,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
电源：1.5,1.5/3.3,2/2.5,2.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：2.6 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.575 V
最小供电电压：1.425 V标称供电电压：1.5 V
表面贴装：YES技术：CMOS
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：23 mm
Base Number Matches：1

XC2VP7-7FG456I 数据手册

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0
R
Virtex-II Pro™ Platform FPGAs:  
Introduction and Overview  
0
0
DS083-1 (v1.0) January 31, 2002  
Advance Product Specification  
•
•
8B /10B encoder and decoder  
Summary of Virtex-II Pro Features  
50Ω /75Ω on-chip selectable transmit and receive  
terminations  
•
High-performance Platform FPGA solution including  
-
Up to sixteen Rocket I/O™ embedded multi-gigabit  
transceiver blocks (based on Mindspeed's  
SkyRail™ technology)  
Up to four IBM® PowerPC® RISC processor blocks  
•
•
•
•
•
•
•
Programmable comma detection  
Channel bonding support (two to sixteen channels)  
Rate matching via insertion/deletion characters  
Four levels of selectable pre-emphasis  
Five levels of output differential voltage  
Per-channel internal loopback modes  
2.5V transceiver supply voltage  
-
•
Based on Virtex™-II Platform FPGA technology  
-
-
-
-
-
-
-
-
Flexible logic resources  
SRAM-based in-system configuration  
Active Interconnect™ technology  
SelectRAM™ memory hierarchy  
Dedicated 18-bit x 18-bit multiplier blocks  
High-performance clock management circuitry  
SelectI/O™-Ultra technology  
PowerPC RISC Core Features  
•
•
•
•
•
•
•
•
Embedded 300+ MHz Harvard architecture core  
Low power consumption: 0.9 mW/MHz  
Five-stage data path pipeline  
Digitally Controlled Impedance (DCI) I/O  
The members and resources of the Virtex-II Pro family are  
shown in Table 1.  
Hardware multiply/divide unit  
Thirty-two 32-bit general purpose registers  
16 KB two-way set-associative instruction cache  
16 KB two-way set-associative data cache  
Memory Management Unit (MMU)  
Rocket I/O Features  
•
Full-duplex serial transceiver (SERDES) capable of  
baud rates from 622 Mb/s to 3.125 Gb/s  
-
64-entry unified Translation Look-aside Buffers  
(TLB)  
•
•
•
80 Gb/s duplex data rate (16 channels)  
Monolithic clock synthesis and clock recovery (CDR)  
-
Variable page sizes (1 KB to 16 MB)  
Fibre Channel, Gigabit Ethernet, 10 Gb Attachment  
Unit Interface (XAUI), and Infiniband-compliant  
transceivers  
•
•
•
•
Dedicated on-chip memory (OCM) interface  
Supports IBM CoreConnect™ bus architecture  
Debug and trace support  
•
8-, 16-, or 32-bit selectable internal FPGA interface  
Timer facilities  
Table 1: Virtex-II Pro FPGA Family Members  
CLB  
(1 CLB = 4 slices = Max 128 bits)  
Block SelectRAM  
Rocket I/O  
Transceiver Processor  
PowerPC  
Maximum 18 X 18 Bit  
Distributed Multiplier  
Max  
Array  
18 Kb Block RAM  
Max  
Device  
XC2VP2  
XC2VP4  
XC2VP7  
XC2VP20  
XC2VP50  
Blocks  
Blocks  
Row x Col Slices  
RAM (Kb)  
Blocks  
Blocks  
(Kb)  
DCMs I/O Pads  
4
4
0
1
1
2
4
16 x 22  
40 x 22  
40 x 34  
56 x 46  
1,408  
3,008  
4,928  
9,280  
44  
12  
12  
216  
4
4
4
8
8
204  
348  
396  
564  
852  
94  
28  
28  
504  
8
154  
44  
44  
792  
8
290  
88  
88  
1,584  
3,888  
16  
88 x 70 22,592  
706  
216  
216  
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS083-1 (v1.0) January 31, 2002  
www.xilinx.com  
1
Advance Product Specification  
1-800-255-7778  
 
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与XC2VP7-7FG456I相关器件

型号 品牌 获取价格 描述 数据表
XC2VP7-7FGG456I XILINX

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 		Field Programmable Gate Array, 1232 CLBs, 1350MHz, CMOS, PBGA456, 1 MM PITCH, FBGA-456
XC2VPX20 XILINX

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 		Platform Flash In-System Programmable Configuration PROMS
XC2VPX20-5FF896C XILINX

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 		Field Programmable Gate Array, 2448 CLBs, 1050MHz, 22032-Cell, CMOS, PBGA896, 31 X 31 MM,
XC2VPX20-5FF896I XILINX

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 		Field Programmable Gate Array, 2448 CLBs, 1050MHz, 22032-Cell, CMOS, PBGA896, 31 X 31 MM,
XC2VPX20-5FFG896C XILINX

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 		Field Programmable Gate Array, 2448 CLBs, 1050MHz, 22032-Cell, CMOS, PBGA896, 31 X 31 MM,
XC2VPX20-7FF896C XILINX

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 		Field Programmable Gate Array, 2448 CLBs, 1350MHz, 22032-Cell, CMOS, PBGA896, 31 X 31 MM,
XC2VPX20-7FFG896C XILINX

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 		Field Programmable Gate Array, 2448 CLBs, 1350MHz, CMOS, PBGA896, 31 X 31 MM, 1 MM PITCH,
XC2VPX70 XILINX

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 		Platform Flash In-System Programmable Configuration PROMS
XC2VPX70-5FF1704C XILINX

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 		Field Programmable Gate Array, 8272 CLBs, 1050MHz, 74448-Cell, CMOS, PBGA1704, 42.50 X 42.
XC2VPX70-5FF1704I XILINX

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 		Field Programmable Gate Array, 8272 CLBs, 1050MHz, 74448-Cell, CMOS, PBGA1704, 42.50 X 42.

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