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XC2VPX20-7FFG896C PDF预览

XC2VPX20-7FFG896C

更新时间: 2024-11-06 19:52:47
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
432页 2498K
描述
Field Programmable Gate Array, 2448 CLBs, 1350MHz, CMOS, PBGA896, 31 X 31 MM, 1 MM PITCH, FLIP CHIP, FBGA-896

XC2VPX20-7FFG896C 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:31 X 31 MM, 1 MM PITCH, FLIP CHIP, FBGA-896针数:896
Reach Compliance Code:not_compliantECCN代码:3A001.A.7.A
HTS代码:8542.39.00.01风险等级:5.78
最大时钟频率:1350 MHzCLB-Max的组合延迟:0.28 ns
JESD-30 代码:S-PBGA-B896JESD-609代码:e1
长度:31 mm湿度敏感等级:4
可配置逻辑块数量:2448端子数量:896
最高工作温度:85 °C最低工作温度:
组织:2448 CLBS封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):245
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:3.4 mm最大供电电压:1.575 V
最小供电电压:1.425 V标称供电电压:1.5 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:31 mmBase Number Matches:1

XC2VPX20-7FFG896C 数据手册

 浏览型号XC2VPX20-7FFG896C的Datasheet PDF文件第2页浏览型号XC2VPX20-7FFG896C的Datasheet PDF文件第3页浏览型号XC2VPX20-7FFG896C的Datasheet PDF文件第4页浏览型号XC2VPX20-7FFG896C的Datasheet PDF文件第5页浏览型号XC2VPX20-7FFG896C的Datasheet PDF文件第6页浏览型号XC2VPX20-7FFG896C的Datasheet PDF文件第7页 
Product Not Recommended For New Designs  
1 Virtex-II Pro and Virtex-II Pro X Platform FPGAs:  
R
Complete Data Sheet  
0
DS083 (v5.0) June 21, 2011  
Product Specification  
Module 1:  
Introduction and Overview  
Module 3:  
DC and Switching Characteristics  
10 pages  
59 pages  
Summary of Features  
General Description  
Architecture  
IP Core and Reference Support  
Device/Package Combinations and Maximum I/O  
Ordering Information  
Electrical Characteristics  
Performance Characteristics  
Switching Characteristics  
Pin-to-Pin Output Parameter Guidelines  
Pin-to-Pin Input Parameter Guidelines  
DCM Timing Parameters  
Source-Synchronous Switching Characteristics  
Module 2:  
Module 4:  
Pinout Information  
Functional Description  
60 pages  
302 pages  
Functional Description: RocketIO™ X Multi-Gigabit  
Transceiver  
Functional Description: RocketIO Multi-Gigabit  
Transceiver  
Functional Description: Processor Block  
Functional Description: PowerPC™ 405 Core  
Functional Description: FPGA  
Pin Definitions  
Pinout Tables  
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FG256/FGG256 Wire-Bond Fine-Pitch BGA Package  
FG456/FGG456 Wire-Bond Fine-Pitch BGA Package  
FG676/FGG676 Wire-Bond Fine-Pitch BGA Package  
FF672 Flip-Chip Fine-Pitch BGA Package  
FF896 Flip-Chip Fine-Pitch BGA Package  
FF1148 Flip-Chip Fine-Pitch BGA Package  
FF1152 Flip-Chip Fine-Pitch BGA Package  
FF1517 Flip-Chip Fine-Pitch BGA Package  
FF1696 Flip-Chip Fine-Pitch BGA Package  
FF1704 Flip-Chip Fine-Pitch BGA Package  
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Input/Output Blocks (IOBs)  
Digitally Controlled Impedance (DCI)  
On-Chip Differential Termination  
Configurable Logic Blocks (CLBs)  
3-State Buffers  
CLB/Slice Configurations  
18-Kb Block SelectRAM™ Resources  
18-Bit x 18-Bit Multipliers  
Global Clock Multiplexer Buffers  
Digital Clock Manager (DCM)  
Routing  
Configuration  
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision  
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.  
© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is  
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.  
DS083 (v5.0) June 21, 2011  
www.xilinx.com  
1
Product Specification  

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