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XC2VPX70-6FF1704I PDF预览

XC2VPX70-6FF1704I

更新时间: 2024-09-16 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
432页 2498K
描述
Field Programmable Gate Array, 8272 CLBs, 1200MHz, 74448-Cell, CMOS, PBGA1704, 42.50 X 42.50 MM, 1 MM PITCH, MS-034AAV-1, FCBGA-1704

XC2VPX70-6FF1704I 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Not Recommended零件包装代码:BGA
包装说明:42.50 X 42.50 MM, 1 MM PITCH, MS-034AAV-1, FCBGA-1704针数:1704
Reach Compliance Code:not_compliantECCN代码:3A001.A.7.A
HTS代码:8542.39.00.01风险等级:5.3
最大时钟频率:1200 MHzCLB-Max的组合延迟:0.32 ns
JESD-30 代码:S-PBGA-B1704JESD-609代码:e0
长度:42.5 mm湿度敏感等级:4
可配置逻辑块数量:8272输入次数:992
逻辑单元数量:74448输出次数:992
端子数量:1704组织:8272 CLBS
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA1704,42X42,40封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:1.5,1.5/3.3,2/2.5,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:3.45 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.575 V
最小供电电压:1.425 V标称供电电压:1.5 V
表面贴装:YES技术:CMOS
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:42.5 mm
Base Number Matches:1

XC2VPX70-6FF1704I 数据手册

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Product Not Recommended For New Designs  
1 Virtex-II Pro and Virtex-II Pro X Platform FPGAs:  
R
Complete Data Sheet  
0
DS083 (v5.0) June 21, 2011  
Product Specification  
Module 1:  
Introduction and Overview  
Module 3:  
DC and Switching Characteristics  
10 pages  
59 pages  
Summary of Features  
General Description  
Architecture  
IP Core and Reference Support  
Device/Package Combinations and Maximum I/O  
Ordering Information  
Electrical Characteristics  
Performance Characteristics  
Switching Characteristics  
Pin-to-Pin Output Parameter Guidelines  
Pin-to-Pin Input Parameter Guidelines  
DCM Timing Parameters  
Source-Synchronous Switching Characteristics  
Module 2:  
Module 4:  
Pinout Information  
Functional Description  
60 pages  
302 pages  
Functional Description: RocketIO™ X Multi-Gigabit  
Transceiver  
Functional Description: RocketIO Multi-Gigabit  
Transceiver  
Functional Description: Processor Block  
Functional Description: PowerPC™ 405 Core  
Functional Description: FPGA  
Pin Definitions  
Pinout Tables  
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FG256/FGG256 Wire-Bond Fine-Pitch BGA Package  
FG456/FGG456 Wire-Bond Fine-Pitch BGA Package  
FG676/FGG676 Wire-Bond Fine-Pitch BGA Package  
FF672 Flip-Chip Fine-Pitch BGA Package  
FF896 Flip-Chip Fine-Pitch BGA Package  
FF1148 Flip-Chip Fine-Pitch BGA Package  
FF1152 Flip-Chip Fine-Pitch BGA Package  
FF1517 Flip-Chip Fine-Pitch BGA Package  
FF1696 Flip-Chip Fine-Pitch BGA Package  
FF1704 Flip-Chip Fine-Pitch BGA Package  
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Input/Output Blocks (IOBs)  
Digitally Controlled Impedance (DCI)  
On-Chip Differential Termination  
Configurable Logic Blocks (CLBs)  
3-State Buffers  
CLB/Slice Configurations  
18-Kb Block SelectRAM™ Resources  
18-Bit x 18-Bit Multipliers  
Global Clock Multiplexer Buffers  
Digital Clock Manager (DCM)  
Routing  
Configuration  
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision  
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.  
© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is  
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.  
DS083 (v5.0) June 21, 2011  
www.xilinx.com  
1
Product Specification  

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