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XC2VPX70-5FFG1704C PDF预览

XC2VPX70-5FFG1704C

更新时间: 2024-11-07 06:31:23
品牌 Logo 应用领域
赛灵思 - XILINX
页数 文件大小 规格书
432页 2498K
描述
Field Programmable Gate Array, 8272 CLBs, 1050MHz, 74448-Cell, CMOS, PBGA1704, 42.50 X 42.50 MM, 1 MM PITCH, MS-034AAV-1, FCBGA-1704

XC2VPX70-5FFG1704C 数据手册

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Product Not Recommended For New Designs  
1 Virtex-II Pro and Virtex-II Pro X Platform FPGAs:  
R
Complete Data Sheet  
0
DS083 (v5.0) June 21, 2011  
Product Specification  
Module 1:  
Introduction and Overview  
Module 3:  
DC and Switching Characteristics  
10 pages  
59 pages  
Summary of Features  
General Description  
Architecture  
IP Core and Reference Support  
Device/Package Combinations and Maximum I/O  
Ordering Information  
Electrical Characteristics  
Performance Characteristics  
Switching Characteristics  
Pin-to-Pin Output Parameter Guidelines  
Pin-to-Pin Input Parameter Guidelines  
DCM Timing Parameters  
Source-Synchronous Switching Characteristics  
Module 2:  
Module 4:  
Pinout Information  
Functional Description  
60 pages  
302 pages  
Functional Description: RocketIO™ X Multi-Gigabit  
Transceiver  
Functional Description: RocketIO Multi-Gigabit  
Transceiver  
Functional Description: Processor Block  
Functional Description: PowerPC™ 405 Core  
Functional Description: FPGA  
Pin Definitions  
Pinout Tables  
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FG256/FGG256 Wire-Bond Fine-Pitch BGA Package  
FG456/FGG456 Wire-Bond Fine-Pitch BGA Package  
FG676/FGG676 Wire-Bond Fine-Pitch BGA Package  
FF672 Flip-Chip Fine-Pitch BGA Package  
FF896 Flip-Chip Fine-Pitch BGA Package  
FF1148 Flip-Chip Fine-Pitch BGA Package  
FF1152 Flip-Chip Fine-Pitch BGA Package  
FF1517 Flip-Chip Fine-Pitch BGA Package  
FF1696 Flip-Chip Fine-Pitch BGA Package  
FF1704 Flip-Chip Fine-Pitch BGA Package  
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Input/Output Blocks (IOBs)  
Digitally Controlled Impedance (DCI)  
On-Chip Differential Termination  
Configurable Logic Blocks (CLBs)  
3-State Buffers  
CLB/Slice Configurations  
18-Kb Block SelectRAM™ Resources  
18-Bit x 18-Bit Multipliers  
Global Clock Multiplexer Buffers  
Digital Clock Manager (DCM)  
Routing  
Configuration  
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision  
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.  
© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is  
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.  
DS083 (v5.0) June 21, 2011  
www.xilinx.com  
1
Product Specification  

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