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XC2VP7-7FFG672C PDF预览

XC2VP7-7FFG672C

更新时间: 2024-11-20 18:19:47
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
432页 2306K
描述
Field Programmable Gate Array, 1232 CLBs, 1350MHz, 11088-Cell, CMOS, PBGA672, 27 X 27 MM, 1 MM PITCH, MS-034AAL-1, FCBGA-672

XC2VP7-7FFG672C 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:End Of Life零件包装代码:BGA
包装说明:BGA, BGA672,26X26,40针数:672
Reach Compliance Code:not_compliantECCN代码:3A991.D
HTS代码:8542.39.00.01Factory Lead Time:12 weeks
风险等级:5.27最大时钟频率:1350 MHz
CLB-Max的组合延迟:0.28 nsJESD-30 代码:S-PBGA-B672
JESD-609代码:e1长度:27 mm
湿度敏感等级:4可配置逻辑块数量:1232
输入次数:396逻辑单元数量:11088
输出次数:396端子数量:672
最高工作温度:85 °C最低工作温度:
组织:1232 CLBS封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA672,26X26,40
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):245电源:1.5,1.5/3.3,2/2.5,2.5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.575 V最小供电电压:1.425 V
标称供电电压:1.5 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:27 mm
Base Number Matches:1

XC2VP7-7FFG672C 数据手册

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Product Not Recommended For New Designs  
1 Virtex-II Pro and Virtex-II Pro X Platform FPGAs:  
R
Complete Data Sheet  
0
DS083 (v5.0) June 21, 2011  
Product Specification  
Module 1:  
Introduction and Overview  
Module 3:  
DC and Switching Characteristics  
10 pages  
59 pages  
Summary of Features  
General Description  
Architecture  
IP Core and Reference Support  
Device/Package Combinations and Maximum I/O  
Ordering Information  
Electrical Characteristics  
Performance Characteristics  
Switching Characteristics  
Pin-to-Pin Output Parameter Guidelines  
Pin-to-Pin Input Parameter Guidelines  
DCM Timing Parameters  
Source-Synchronous Switching Characteristics  
Module 2:  
Module 4:  
Pinout Information  
Functional Description  
60 pages  
302 pages  
Functional Description: RocketIO™ X Multi-Gigabit  
Transceiver  
Functional Description: RocketIO Multi-Gigabit  
Transceiver  
Functional Description: Processor Block  
Functional Description: PowerPC™ 405 Core  
Functional Description: FPGA  
Pin Definitions  
Pinout Tables  
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FG256/FGG256 Wire-Bond Fine-Pitch BGA Package  
FG456/FGG456 Wire-Bond Fine-Pitch BGA Package  
FG676/FGG676 Wire-Bond Fine-Pitch BGA Package  
FF672 Flip-Chip Fine-Pitch BGA Package  
FF896 Flip-Chip Fine-Pitch BGA Package  
FF1148 Flip-Chip Fine-Pitch BGA Package  
FF1152 Flip-Chip Fine-Pitch BGA Package  
FF1517 Flip-Chip Fine-Pitch BGA Package  
FF1696 Flip-Chip Fine-Pitch BGA Package  
FF1704 Flip-Chip Fine-Pitch BGA Package  
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Input/Output Blocks (IOBs)  
Digitally Controlled Impedance (DCI)  
On-Chip Differential Termination  
Configurable Logic Blocks (CLBs)  
3-State Buffers  
CLB/Slice Configurations  
18-Kb Block SelectRAM™ Resources  
18-Bit x 18-Bit Multipliers  
Global Clock Multiplexer Buffers  
Digital Clock Manager (DCM)  
Routing  
Configuration  
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision  
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.  
© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is  
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.  
DS083 (v5.0) June 21, 2011  
www.xilinx.com  
1
Product Specification  

XC2VP7-7FFG672C 替代型号

型号 品牌 替代类型 描述 数据表
XC2VP7-6FFG672I XILINX

完全替代

Field Programmable Gate Array, 1232 CLBs, 1200MHz, 11088-Cell, CMOS, PBGA672, 27 X 27 MM,

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