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XC2VP50-7FFG1148I PDF预览

XC2VP50-7FFG1148I

更新时间: 2024-09-16 05:16:15
品牌 Logo 应用领域
赛灵思 - XILINX 现场可编程门阵列可编程逻辑
页数 文件大小 规格书
408页 2432K
描述
Field Programmable Gate Array, 5904 CLBs, 1350MHz, CMOS, PBGA1148, 1 MM PITCH, FLIP CHIP, FBGA-1148

XC2VP50-7FFG1148I 数据手册

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Virtex-II Pro™ Platform FPGAs:  
Complete Data Sheet  
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DS083 March 9, 2004  
Product Specification  
This document includes all four modules of the Virtex-II Pro Platform FPGA data sheet.  
Module 1:  
Introduction and Overview  
Module 3:  
DC and Switching Characteristics  
DS083-1 (v3.1.1) March 9, 2004  
8 pages  
DS083-3 (v3.1.1) March 9, 2004  
52 pages  
Summary of Features  
Electrical Characteristics  
General Description  
Architecture  
IP Core and Reference Support  
Device/Package Combinations and Maximum I/O  
Ordering Information  
Performance Characteristics  
Switching Characteristics  
Pin-to-Pin Output Parameter Guidelines  
Pin-to-Pin Input Parameter Guidelines  
DCM Timing Parameters  
Module 2:  
Functional Description  
Module 4:  
Pinout Information  
DS083-2 (v3.1.1) March 9, 2004  
48 pages  
DS083-4 (v3.1.1) March 9, 2004  
299 pages  
Functional Description: RocketIO™ Multi-Gigabit  
Transceiver  
Pin Definitions  
Pinout Tables  
Functional Description: Processor Block  
Functional Description: PowerPC™ 405 Core  
Functional Description: FPGA  
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FG256 Wire-Bond Fine-Pitch BGA Package  
FG456 Wire-Bond Fine-Pitch BGA Package  
FG676 Wire-Bond Fine-Pitch BGA Package  
FF672 Flip-Chip Fine-Pitch BGA Package  
FF896 Flip-Chip Fine-Pitch BGA Package  
FF1148 Flip-Chip Fine-Pitch BGA Package  
FF1152 Flip-Chip Fine-Pitch BGA Package  
FF1517 Flip-Chip Fine-Pitch BGA Package  
FF1696 Flip-Chip Fine-Pitch BGA Package  
FF1704 Flip-Chip Fine-Pitch BGA Package  
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Input/Output Blocks (IOBs)  
Digitally Controlled Impedance (DCI)  
On-Chip Differential Termination  
Configurable Logic Blocks (CLBs)  
3-State Buffers  
CLB/Slice Configurations  
18-Kb Block SelectRAM™ Resources  
18-Bit x 18-Bit Multipliers  
Global Clock Multiplexer Buffers  
Digital Clock Manager (DCM)  
Routing  
Configuration  
IMPORTANT NOTE: The Virtex-II Pro Platform FPGA data sheet is created and published in separate modules. This  
complete version is provided for easy downloading and searching of the complete document. Page, figure, and table  
numbers begin at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks"  
pane for easy navigation in this volume.  
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS083 March 9, 2004  
www.xilinx.com  
Product Specification  
1-800-255-7778  

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