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XC2V10000-5FF1152C PDF预览

XC2V10000-5FF1152C

更新时间： 2024-09-20 14:38:47
品牌 Logo 应用领域
赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
7页 57K
描述
Field Programmable Gate Array, 15360 CLBs, 10000000 Gates, 880MHz, CMOS, PBGA1152, 1 MM PITCH, FLIP CHIP, FBGA-1152

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XC2V10000-5FF1152C 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：1 MM PITCH, FLIP CHIP, FBGA-1152针数：1152
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.92Is Samacsys：N
最大时钟频率：880 MHzCLB-Max的组合延迟：0.39 ns
JESD-30 代码：S-PBGA-B1152JESD-609代码：e0
长度：35 mm湿度敏感等级：4
可配置逻辑块数量：15360等效关口数量：10000000
端子数量：1152最高工作温度：85 °C
最低工作温度：组织：15360 CLBS, 10000000 GATES
封装主体材料：PLASTIC/EPOXY封装代码：HBGA
封装形状：SQUARE封装形式：GRID ARRAY, HEAT SINK/SLUG
峰值回流温度（摄氏度）：225可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：3.4 mm
最大供电电压：1.575 V最小供电电压：1.425 V
标称供电电压：1.5 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：35 mm
Base Number Matches：1

XC2V10000-5FF1152C 数据手册

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0
R
Virtex-II 1.5V  
Field-Programmable Gate Arrays  
0
0
DS031-1 (v1.5) April 2, 2001  
Advance Product Specification  
®
Summary of Virtex -II Features  
•
•
Industry First Platform FPGA Solution  
IP-Immersion™ Architecture  
-
XCITE™ Digitally Controlled Impedance (DCI) I/O:  
on-chip termination resistors for single-ended I/O  
standards  
PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz  
compliance  
-
-
-
Densities from 40K to 10M system gates  
420 MHz internal clock speed (Advance Data)  
840+ Mb/s I/O (Advance Data)  
-
-
Differential Signaling  
•
SelectRAM™ Memory Hierarchy  
·
840 Mb/s Low-Voltage Differential Signaling I/O  
(LVDS) with current mode drivers  
Bus LVDS I/O  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
-
3.5 Mb of True Dual-Port™ RAM in 18-Kbit block  
SelectRAM resources  
·
·
-
-
Up to 1.9 Mb of distributed SelectRAM resources  
High-performance interfaces to external memory  
·
·
·
400 Mb/s DDR-SDRAM interface (Advance Data)  
400 Mb/s FCRAM interface (Advance Data)  
333 Mb/s QDR™-SRAM interface (Advance  
Data)  
·
Low-Voltage Positive Emitter-Coupled Logic  
(LVPECL) I/O  
Built-in DDR Input and Output registers  
·
-
Proprietary high-performance SelectLink™  
Technology  
·
600 Mb/s Sigma RAM interface (Advance Data)  
•
•
Arithmetic Functions  
·
·
·
High-bandwidth data path  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
-
-
Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
•
•
Supported by Xilinx Foundation™ and Alliance™  
Series Development Systems  
Flexible Logic Resources  
-
Up to 122,880 internal registers / latches with  
Clock Enable  
-
-
-
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
-
Up to 122,880 look-up tables (LUTs) or cascadable  
16-bit shift registers  
-
-
Wide multiplexers and wide-input function support  
Horizontal cascade chain and Sum-of-Products  
support  
SRAM-Based In-System Configuration  
-
-
Fast SelectMAP™ configuration  
Triple Data Encryption Standard (DES) security  
option (Bitstream Encryption)  
IEEE1532 support  
Partial reconfiguration  
Unlimited re-programmability  
Readback capability  
-
Internal 3-state bussing  
-
-
-
-
•
High-Performance Clock Management Circuitry  
-
Up to 12 DCM (Digital Clock Manager) modules  
·
·
·
·
Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
EMI reduction  
•
•
Power-Down Mode  
0.15 µm 8-Layer Metal process with 0.12 µm  
high-speed transistors  
-
16 global clock multiplexer buffers  
•
•
Active Interconnect™ Technology  
•
1.5 V (VCCINT) core power supply, dedicated 3.3 V  
VCCAUX auxiliary and VCCO I/O power supplies  
-
-
Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of  
fanout  
•
•
IEEE 1149.1 compatible boundary-scan logic support  
Flip-Chip and Wire-Bond Ball Grid Array (BGA)  
packages in three standard fine pitches (0.80mm,  
1.00mm, and 1.27mm)  
SelectI/O-Ultra™ Technology  
-
-
Up to 1,108 user I/Os  
19 single-ended standards and six differential  
•
100% factory tested  
standards  
-
Programmable sink current (2 mA to 24 mA) per  
I/O  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS031-1 (v1.5) April 2, 2001  
Advance Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
1
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