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XC2S300E-6FG456I

更新时间： 2024-09-19 22:41:19
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赛灵思 - XILINX 现场可编程门阵列可编程逻辑栅时钟
页数 文件大小 规格书
4页 113K
描述
Spartan-IIE 1.8V FPGA Family

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XC2S300E-6FG456I 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：FBGA-456针数：456
Reach Compliance Code：not_compliantECCN代码：3A991.D
HTS代码：8542.39.00.01风险等级：5.79
Is Samacsys：N其他特性：MAXIMUM USABLE GATES = 300000
最大时钟频率：357 MHzCLB-Max的组合延迟：0.47 ns
JESD-30 代码：S-PBGA-B456JESD-609代码：e0
长度：23 mm湿度敏感等级：3
可配置逻辑块数量：1536等效关口数量：93000
输入次数：329逻辑单元数量：6912
输出次数：329端子数量：456
组织：1536 CLBS, 93000 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA456,22X22,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：225电源：1.5/3.3,1.8 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.6 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.89 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：23 mmBase Number Matches：1

XC2S300E-6FG456I 数据手册

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0
Spartan-IIE 1.8V FPGA Family:  
Introduction and Ordering  
Information  
R
0
0
DS077-1 (v1.0) November 15, 2001  
Preliminary Product Specification  
•
System level features  
Introduction  
-
SelectRAM+™ hierarchical memory:  
The Spartan™-IIE 1.8V Field-Programmable Gate Array  
family gives users high performance, abundant logic  
resources, and a rich feature set, all at an exceptionally low  
price. The five-member family offers densities ranging from  
50,000 to 300,000 system gates, as shown in Table 1. Sys-  
tem performance is supported beyond 200 MHz.  
·
·
·
16 bits/LUT distributed RAM  
Configurable 4K-bit true dual-port block RAM  
Fast interfaces to external RAM  
-
Fully 3.3V PCI compliant to 64 bits at 66 MHz and  
CardBus compliant  
-
-
-
-
-
-
-
-
-
Low-power segmented routing architecture  
Full readback ability for verification/observability  
Dedicated carry logic for high-speed arithmetic  
Efficient multiplier support  
Cascade chain for wide-input functions  
Abundant registers/latches with enable, set, reset  
Four dedicated DLLs for advanced clock control  
Four primary low-skew global clock distribution nets  
IEEE 1149.1 compatible boundary scan logic  
Spartan-IIE devices deliver more gates, I/Os, and features  
per dollar than other FPGAs by combining advanced pro-  
cess technology with a streamlined architecture based on  
the proven Virtex™-E platform. Features include block RAM  
(to 64K bits), distributed RAM (to 98,304 bits), 19 selectable  
I/O standards, and four DLLs (Delay-Locked Loops). Fast,  
predictable interconnect means that successive design iter-  
ations continue to meet timing requirements.  
The Spartan-IIE family is a superior alternative to  
mask-programmed ASICs. The FPGA avoids the initial cost,  
lengthy development cycles, and inherent risk of  
conventional ASICs. Also, FPGA programmability permits  
design upgrades in the field with no hardware replacement  
necessary (impossible with ASICs).  
•
Versatile I/O and packaging  
-
-
-
Low cost packages available in all densities  
Family footprint compatibility in common packages  
19 high-performance interface standards, including  
LVDS and LVPECL  
-
Up to 120 differential I/O pairs that can be input,  
output, or bidirectional  
Features  
-
Zero hold time simplifies system timing  
•
Second generation ASIC replacement technology  
•
Fully supported by powerful Xilinx ISE development  
system  
-
-
-
Densities as high as 6,912 logic cells with up to  
300,000 system gates  
Fully automatic mapping, placement, and routing  
Integrated with design entry and verification tools  
-
Streamlined features based on Virtex-E  
architecture  
-
-
Unlimited in-system reprogrammability  
Very low cost  
Table 1: Spartan-IIE FPGA Family Members  
Typical  
CLB  
Maximum  
Maximum  
Logic System Gate Range  
Array  
Total  
Available Differential Distributed  
Block  
Device  
Cells  
1,728  
2,700  
3,888  
5,292  
6,912  
(Logic and RAM)  
23,000 - 50,000  
37,000 - 100,000  
52,000 - 150,000  
71,000 - 200,000  
93,000 - 300,000  
(R x C) CLBs  
User I/O  
182  
I/O Pairs  
84  
RAM Bits  
24,576  
38,400  
55,296  
75,264  
98,304  
RAM Bits  
XC2S50E  
XC2S100E  
XC2S150E  
XC2S200E  
XC2S300E  
16 x 24  
20 x 30  
24 x 36  
384  
600  
864  
32K  
40K  
48K  
56K  
64K  
202  
86  
263  
114  
28 x 42 1,176  
32 x 48 1,536  
289  
120  
329  
120  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS077-1 (v1.0) November 15, 2001  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
1234

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XC2S300E-6FG456I 替代型号

型号 品牌 替代类型 描述 数据表
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