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XC2C32A-4QFG32C PDF预览

XC2C32A-4QFG32C

更新时间： 2024-11-10 14:36:51
品牌 Logo 应用领域
赛灵思 - XILINX 时钟光电二极管可编程逻辑
页数 文件大小 规格书
14页 305K
描述
Flash PLD, 4ns, 32-Cell, CMOS, PDSO32, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, QFN-32

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XC2C32A-4QFG32C 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：SON, LCC32,.2SQ,20针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：5.17其他特性：REAL DIGITAL DESIGN TECHNOLOGY
最大时钟频率：450 MHz系统内可编程：YES
JESD-30 代码：S-PDSO-N32JESD-609代码：e3
JTAG BST：YES长度：5 mm
湿度敏感等级：3I/O 线路数量：21
宏单元数：32端子数量：32
最高工作温度：70 °C最低工作温度：
组织：21 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：SON
封装等效代码：LCC32,.2SQ,20封装形状：SQUARE
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：1.5/3.3,1.8 V可编程逻辑类型：FLASH PLD
传播延迟：4 ns认证状态：Not Qualified
座面最大高度：1 mm子类别：Programmable Logic Devices
最大供电电压：1.9 V最小供电电压：1.7 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：5 mm
Base Number Matches：1

XC2C32A-4QFG32C 数据手册

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XC2C32A CoolRunner-II CPLD  
0
0
DS310 (v2.1) November 6, 2008  
Product Specification  
Features  
Description  
•
•
•
Optimized for 1.8V systems  
The CoolRunner™-II 32-macrocell device is designed for  
both high performance and low power applications. This  
lends power savings to high-end communication equipment  
and high speed to battery operated devices. Due to the low  
power stand-by and dynamic operation, overall system reli-  
ability is improved.  
-
-
As fast as 3.8 ns pin-to-pin logic delays  
As low as 12 μA quiescent current  
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation: 1.5V through 3.3V  
This device consists of two Function Blocks interconnected  
by a low power Advanced Interconnect Matrix (AIM). The  
AIM feeds 40 true and complement inputs to each Function  
Block. The Function Blocks consist of a 40 by 56 P-term  
PLA and 16 macrocells which contain numerous configura-  
tion bits that allow for combinational or registered modes of  
operation.  
Available in multiple package options  
-
-
-
-
32-land QFN with 21 user I/Os  
44-pin VQFP with 33 user I/Os  
56-ball CP BGA with 33 user I/Os  
Pb-free available for all packages  
•
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain, and programmable grounds. A Schmitt trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers can be  
configured as "direct input" registers to store signals directly  
from input pins.  
·
-
-
-
-
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Two separate I/O banks  
RealDigital 100% CMOS product term generation  
Flexible clocking modes  
Optional DualEDGE triggered registers  
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as a  
synchronous clock source. Macrocell registers can be indi-  
vidually configured to power up to the zero or one state. A  
global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asynchro-  
nous set/reset, and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
·
·
Multiple global output enables  
Global set/reset  
-
Efficient control term clocks, output enables and  
set/resets for each macrocell and shared across  
function blocks  
Advanced design security  
Open-drain output option for Wired-OR and LED  
drive  
Optional configurable grounds on unused I/Os  
Optional bus-hold, 3-state, or weak pullup on  
selected I/O pins  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
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The CoolRunner-II 32-macrocell CPLD is I/O compatible  
with standard LVTTL and LVCMOS18, LVCMOS25, and  
LVCMOS33 (see Table 1). This device is also 1.5V I/O com-  
patible with the use of Schmitt-trigger inputs.  
-
-
PLA architecture  
·
·
Superior pinout retention  
100% product term routability across function  
block  
Another feature that eases voltage translation is I/O bank-  
ing. Two I/O banks are available on the CoolRunner-II 32A  
macrocell device that permit easy interfacing to 3.3V, 2.5V,  
1.8V, and 1.5V devices.  
-
Hot pluggable  
Refer to the CoolRunner™-II family data sheet for the archi-  
tecture description.  
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS310 (v2.1) November 6, 2008  
Product Specification  
www.xilinx.com  
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XC2C32A-4QFG32C 替代型号

型号 品牌 替代类型 描述 数据表
XC2C32A-6QFG32I XILINX

功能相似

 Flash PLD, 6ns, 32-Cell, CMOS, PDSO32, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, QFN-32

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XC2C32A-6CPG56C XILINX

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XC2C32A-6QFG32I XILINX

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 		Flash PLD, 6ns, 32-Cell, CMOS, PDSO32, 5 X 5 MM, 0.50 MM PITCH, LEAD FREE, QFN-32
XC2C32A-6VQ44I XILINX

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XC2C32A-6VQG44C XILINX

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 		Flash PLD, 6ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
XC2C32A-6VQG44I XILINX

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 		Flash PLD, 6ns, 32-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
XC2C384 XILINX

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 		CoolRunner-II CPLD Family
XC2C384-10FG324C XILINX

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