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XC2C32A CoolRunner-II CPLD
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DS310 (v1.1) August 30, 2004
Advance Product Specification
Features
Description
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Optimized for 1.8V systems
The CoolRunner-II 32-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
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As fast as 3.0 ns pin-to-pin logic delays
As low as 12 µA quiescent current
Industry’s best 0.18 micron CMOS CPLD
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Optimized architecture for effective logic synthesis
Multi-voltage I/O operation: 1.5V through 3.3V
This device consists of two Function Blocks interconnected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Available in multiple package options
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32-land QFN with 21 user I/O
44-pin PLCC with 33 user I/O
44-pin VQFP with 33 user I/O
56-ball CP BGA with 33 user I/O
Pb-free available for all packages
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Advanced system features
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
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Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
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IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
I/O Banking
RealDigital 100% CMOS product term generation
Flexible clocking modes
Optional DualEDGE triggered registers
Global signal options with macrocell control
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Multiple global clocks with phase selection per
macrocell
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
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Multiple global output enables
Global set/reset
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Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
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Advanced design security
Open-drain output option for Wired-OR and LED
drive
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Optional configurable grounds on unused I/Os
Optional bus-hold, 3-state or weak pullup on
selected I/O pins
The CoolRunner-II 32-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Table 1). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
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Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
PLA architecture
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Superior pinout retention
100% product term routability across function
block
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Hot pluggable
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS310 (v1.1) August 30, 2004
www.xilinx.com
1
Advance Product Specification
1-800-255-7778
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