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XA2943BGALT PDF预览

XA2943BGALT

更新时间： 2024-09-19 02:52:23
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德州仪器 - TI /
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93页 2256K
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AWR2944 Single-Chip 76- and 81-GHz FMCW Radar Sensor

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XA2943BGALT 数据手册

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AWR2944  
SWRS273 – NOVEMBER 2021  
AWR2944 Single-Chip 76- and 81-GHz FMCW Radar Sensor  
•
On Chip RAM  
– 3.5 – 4 MBytes (AWR2943 with 3.5MB &  
AWR2944 with 4MB)  
1 Features  
•
FMCW transceiver  
– Integrated PLL, Transmitter, Receiver,  
Baseband and ADC  
– Memory space split between DSP, MCU, and  
shared L3  
– 76-81 GHz coverage with 5GHz available  
Bandwidth  
•
Device Security (on select part numbers)  
– Programmable embedded Hardware security  
module (HSM)  
– Secure authenticated and encrypted boot  
support  
– Customer programmable root keys, symmetric  
keys (256 bit), Asymmetric keys (up to RSA-4K  
or ECC-512) with Key revocation capability  
– Crypto hardware accelerators - PKA with ECC,  
AES (up to 256 bit), SHA (up to 512 bit), TRNG/  
DRGB  
Functional Safety-Compliant targeted  
– Developed for functional safety applications  
– Documentation will be available to aid ISO  
26262 functional safety system design  
– Hardware integrity up to ASIL B targeted  
AEC-Q100 qualified  
Advanced Features  
– Embedded self-monitoring with no external  
processor involvement  
– Embedded interference detection capability  
Power Management  
– On die LDO network for enhanced PSRR  
– LVCMOS IO supports dual voltage 3.3V/1.8V  
Clock source  
– 4 Receive and 3 – 4 Transmit channels  
(AWR2943 with 3 channels & AWR2944 with  
4 channels) for PCB interface to antennas  
– Per Transmit phase shifter  
– Ultra-Accurate Chirp engine based on  
fractional-N PLL  
– TX power  
•
12 dBm  
– RX noise Figure  
13 dB  
– Phase Noise @ 1MHz  
•
•
•
•
-96 dBc/Hz [76 to 77 GHz]  
-95 dBc/Hz [76 to 81 GHz]  
•
•
Built in calibration and Self-Test  
•
•
– Built in Firmware (ROM)  
– Self-calibrating system across process and  
temperature  
Processing Elements  
– ARM R5F ® Core [Supports lock step  
operation]  
– TI Digital Signal Processor C66x  
– TI Radar Hardware Accelerator (HWA2.0) for  
operations like FFT, Log Magnitude, memory  
compression etc..  
– Multiple EDMA Instances for Data Movement  
Host Interface  
•
•
– 40 MHz crystal with internal oscillator  
– Supports external oscillator at 40 MHz  
– Supports externally driven clock (Square/Sine)  
at 40 MHz  
Cost Reduced Hardware Design  
– 0.65mm pitch, 12 mm × 12 mm flip chip BGA  
package for easy assembly and low cost PCB  
design  
– Small solution size  
Supports Automotive Temperature Operating  
•
– 2x CAN-FD  
•
•
– 10/100 Mbps RGMII/RMII/MII Ethernet  
Supports a Serial Flash Memory Interface (loading  
user application from QSPI flash memory)  
Other Interfaces Available to User Application  
– Up to 9 ADC Channels  
– 2 SPIs  
– 4 UARTs  
– I2C  
– GPIOs  
•
•
Range  
– Operating junction temperature range: –40°C to  
140°C  
– 3 EPWMs  
– 4-Lane Aurora LVDS Interface for Raw ADC  
Data and Debug Instrumentation  
– CSI2 Rx interface to enable playback of the  
captured data  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change  
without notice.  
 
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