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R
XA2C128 CoolRunner-II
Automotive CPLD
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DS554 (v1.1) May 5, 2007
Product Specification
Refer to the CoolRunner™-II Automotive CPLD family data
sheet for architecture description.
Features
•
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
WARNING: Programming temperature range of
TA = 0° C to +70° C.
•
Guaranteed to meet full electrical specifications over
TA = -40° C to +105° C with TJ Maximum = +125° C
Description
(Q-grade)
The CoolRunner-II Automotive 128-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved
•
•
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
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Optimized architecture for effective logic synthesis
Multi-voltage I/O operation — 1.5V to 3.3V
•
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Available in the following package options
This device consists of eight Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
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100-pin VQFP with 80 user I/O
132-ball CP (0.5mm) BGA with 100 user I/O
Pb-free only for all packages
Advanced system features
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Fastest in system programming
1.8V ISP using IEEE 1532 (JTAG) interface
·
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IEEE1149.1 JTAG Boundary Scan Test
Optional Schmitt-trigger input (per pin)
Unsurpassed low power management
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as direct input registers to store signals directly
from input pins.
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DataGATE enable (DGE) signal control
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Two separate I/O banks
RealDigital 100% CMOS product term generation
Flexible clocking modes
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Optional DualEDGE triggered registers
Clock divider (divide by 2,4,6,8,10,12,14,16)
CoolCLOCK
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Global signal options with macrocell control
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Multiple global clocks with phase selection per
macrocell
Multiple global output enables
Global set/reset
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
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·
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Advanced design security
Open-drain output option for Wired-OR and LED
drive
PLA architecture
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Superior pinout retention
100% product term routability across function
block
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
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Optional bus-hold, 3-state or weak pull-up on
selected I/O pins
Optional configurable grounds on unused I/Os
Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
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Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
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Hot pluggable
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS554 (v1.1) May 5, 2007
www.xilinx.com
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Product Specification
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