5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 可编程逻辑器件> XA2C32A-6VQG44I
XA2C32A-6VQG44I PDF预览

XA2C32A-6VQG44I

更新时间： 2024-11-08 03:14:51
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑器件输入元件
页数 文件大小 规格书
14页 326K
描述
CoolRunner-II Automotive CPLD

阅读下载

中文翻译

获取价格

XA2C32A-6VQG44I 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TQFP, TQFP44,.47SQ,32针数：44
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.56
Is Samacsys：N其他特性：REAL DIGITAL DESIGN TECHNOLOGY
系统内可编程：YESJESD-30 代码：S-PQFP-G44
JESD-609代码：e3JTAG BST：YES
长度：10 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：33
宏单元数：32端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 33 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装等效代码：TQFP44,.47SQ,32封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE峰值回流温度（摄氏度）：260
电源：1.5/3.3,1.8 V可编程逻辑类型：FLASH PLD
传播延迟：6 ns认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：1.2 mm
子类别：Programmable Logic Devices最大供电电压：1.9 V
最小供电电压：1.7 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：10 mmBase Number Matches：1

XA2C32A-6VQG44I 数据手册

 浏览型号XA2C32A-6VQG44I的Datasheet PDF文件第2页浏览型号XA2C32A-6VQG44I的Datasheet PDF文件第3页浏览型号XA2C32A-6VQG44I的Datasheet PDF文件第4页浏览型号XA2C32A-6VQG44I的Datasheet PDF文件第5页浏览型号XA2C32A-6VQG44I的Datasheet PDF文件第6页浏览型号XA2C32A-6VQG44I的Datasheet PDF文件第7页 
0
R
XA2C32A CoolRunner-II  
Automotive CPLD  
0
0
DS552 (v1.1) May 5, 2007  
Product Specification  
Features  
Description  
•
AEC-Q100 device qualification and full PPAP support  
available in both I-grade and extended temperature  
Q-grade  
The CoolRunner™-II Automotive 32-macrocell device is  
designed for both high performance and low power applica-  
tions. This lends power savings to high-end communication  
equipment and high speed to battery operated devices. Due  
to the low power stand-by and dynamic operation, overall  
system reliability is improved  
•
Guaranteed to meet full electrical specifications over  
TA = -40° C to +105° C with TJ Maximum = +125° C  
(Q-grade)  
This device consists of two Function Blocks interconnected  
by a low power Advanced Interconnect Matrix (AIM). The  
AIM feeds 40 true and complement inputs to each Function  
Block. The Function Blocks consist of a 40 by 56 P-term  
PLA and 16 macrocells which contain numerous configura-  
tion bits that allow for combinational or registered modes of  
operation.  
•
•
Optimized for 1.8V systems  
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation: 1.5V through 3.3V  
•
•
Available in Pb-free 44-pin VQFP with 33 user I/O  
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain and programmable grounds. A Schmitt trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers may be  
configured as "direct input" registers to store signals directly  
from input pins.  
·
-
-
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Two separate I/O banks  
RealDigital 100% CMOS product term generation  
Flexible clocking modes  
·
Optional DualEDGE triggered registers  
-
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Macrocell registers can be  
individually configured to power up to the zero or one state.  
A global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asynchro-  
nous set/reset and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
·
·
Multiple global output enables  
Global set/reset  
-
Efficient control term clocks, output enables and  
set/resets for each macrocell and shared across  
function blocks  
Advanced design security  
Open-drain output option for Wired-OR and LED  
drive  
Optional configurable grounds on unused I/Os  
Optional bus-hold, 3-state or weak pullup on  
selected I/O pins  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
PLA architecture  
·
·
-
-
-
-
The CoolRunner-II Automotive 32-macrocell CPLD is I/O  
compatible with standard LVTTL and LVCMOS18,  
LVCMOS25, and LVCMOS33 (see Table 1). This device is  
also 1.5V I/O compatible with the use of Schmitt-trigger  
inputs.  
-
-
Superior pinout retention  
100% product term routability across function  
block  
Another feature that eases voltage translation is I/O bank-  
ing. Two I/O banks are available on the CoolRunner-II Auto-  
motive 32-macrocell device that permit easy interfacing to  
3.3V, 2.5V, 1.8V, and 1.5V devices.  
-
Hot pluggable  
Refer to the CoolRunner™-II Automotive CPLD family data  
sheet for architecture description.  
WARNING: Programming temperature range of  
TA = 0° C to +70° C  
© 2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS552 (v1.1) May 5, 2007  
www.xilinx.com  
1
Product Specification  
1234567...14

中文翻译

下载PDF

XA2C32A-6VQG44I 替代型号

型号 品牌 替代类型 描述 数据表
XA2C32A-7VQG44Q XILINX

完全替代

 CoolRunner-II Automotive CPLD

与XA2C32A-6VQG44I相关器件

型号 品牌 获取价格 描述 数据表
XA2C32A-7VQG44Q XILINX

获取价格

 		CoolRunner-II Automotive CPLD
XA2C64A-7VQG100I XILINX

获取价格

 		Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, VQFP-100
XA2C64A-7VQG44I XILINX

获取价格

 		暂无描述
XA2C64A-8VQG44Q XILINX

获取价格

 		Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, VQFP-44
XA2S100E-6TQ144I XILINX

获取价格

 		Field Programmable Gate Array, 600 CLBs, 357MHz, 2700-Cell, CMOS, PQFP144, PLASTIC, TQFP-1
XA2S100E-6TQ144Q XILINX

获取价格

 		Field Programmable Gate Array, 600 CLBs, 357MHz, 2700-Cell, CMOS, PQFP144, PLASTIC, TQFP-1
XA2S150E-6FT256I XILINX

获取价格

 		Field Programmable Gate Array, 864 CLBs, 357MHz, 3888-Cell, CMOS, PBGA256, FBGA-256
XA2S150E-6FT256Q XILINX

获取价格

 		Field Programmable Gate Array, 864 CLBs, 357MHz, 3888-Cell, CMOS, PBGA256, FBGA-256
XA2S200E-6FT256I XILINX

获取价格

 		Field Programmable Gate Array, 1176 CLBs, 357MHz, 5292-Cell, CMOS, PBGA256, FBGA-256
XA2S200E-6FT256Q XILINX

获取价格

 		暂无描述

与XA2C32A-6VQG44I相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证