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WS1M8V-100CIA PDF预览

WS1M8V-100CIA

更新时间: 2024-02-06 14:34:01
品牌 Logo 应用领域
美高森美 - MICROSEMI 静态存储器内存集成电路
页数 文件大小 规格书
5页 138K
描述
Standard SRAM, 1MX8, 100ns, CMOS, CDIP32, 0.600 INCH, SINGLE CAVITY, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-32

WS1M8V-100CIA 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:0.600 INCH, SINGLE CAVITY, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-32Reach Compliance Code:unknown
风险等级:5.7最长访问时间:100 ns
JESD-30 代码:R-CDIP-T32JESD-609代码:e0
内存密度:8388608 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:32字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX8封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:5.13 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15.24 mmBase Number Matches:1

WS1M8V-100CIA 数据手册

 浏览型号WS1M8V-100CIA的Datasheet PDF文件第2页浏览型号WS1M8V-100CIA的Datasheet PDF文件第3页浏览型号WS1M8V-100CIA的Datasheet PDF文件第4页浏览型号WS1M8V-100CIA的Datasheet PDF文件第5页 
WS1M8V-XCX  
2x512Kx8 DUALITHIC™ SRAM ADVANCED*  
FEATURES  
Access Times 70, 85, 100ns  
PIN CONFIGURATION FOR WS1M8V-XCX  
Evolutionary, Corner Power/Ground Pinout  
Packaging:  
32 DIP  
TOP VIEW  
A18  
A16  
A14  
A12  
A7  
1
32  
V
CC  
• 32 pin, Hermetic Ceramic DIP (Package 300)  
Organized as two banks of 512Kx8  
Commercial, Industrial and Military Temperature Ranges  
3.3V Power Supply  
2
31 A15  
30 A17  
29 WE  
28 A13  
27 A8  
3
4
5
A6  
6
A5  
7
26 A9  
Low Power CMOS  
A4  
8
25 A11  
24 CS2  
23 A10  
22 CS1  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
A3  
9
TTL Compatible Inputs and Outputs  
Output Enable Internally tied to GND.  
A2  
10  
11  
12  
13  
14  
15  
16  
A1  
A0  
This data sheet describes a product that may or may not be under  
*
I/O0  
I/O1  
I/O2  
GND  
development and is subject to change or cancellation without notice.  
PIN DESCRIPTION  
A0-18  
Address Inputs  
Data Input/Output  
Chip Selects  
I/O0-7  
CS1-2  
WE  
Write Enable  
VCC  
+3.3V Power Supply  
Ground  
GND  
BLOCK DIAGRAM  
I/O0-7  
WE  
0-18  
A
512K x 8  
512K x 8  
CS1(1)  
CS2(1)  
NOTE:  
1. CS1 and CS2 are used to select the lower and upper 512Kx8 of the  
device. CS1 and CS2 must not be enabled at the same time.  
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
February 2000 Rev. 2  

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