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W3EG7264S202BD4MG PDF预览

W3EG7264S202BD4MG

更新时间: 2024-11-01 13:15:35
品牌 Logo 应用领域
WEDC 存储内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
13页 197K
描述
DDR DRAM Module, 64MX72, 0.75ns, CMOS, ROHS COMPLIANT, SO-DIMM-200

W3EG7264S202BD4MG 数据手册

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W3EG7264S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY*  
512MB – 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL  
FEATURES  
DESCRIPTION  
Double-data-rate architecture  
The W3EG7264S is a 2x32Mx72 Double Data Rate  
SDRAM memory module based on 512Mb DDR SDRAM  
components. The module consists of nine 64Mx8 DDR  
SDRAMs stacked in 54 pin TSOP packages mounted on  
a 200 pin FR4 substrate. This module is structured as 2  
Ranks of 64Mx72 DDR SDRAM.  
DDR200, DDR266 DDR333  
• JEDEC design specifications  
Bi-directional data strobes (DQS)  
Differential clock inputs (CK & CK#)  
Programmable Read Latency 2,2.5 (clock)  
Programmable Burst Length (2,4,8)  
Programmable Burst type (sequential & interleave)  
Edge aligned data output, center aligned data input  
Auto and self refresh  
Synchronous design allows precise cycle control with the  
use of system clock. Data I/O transactions are possible on  
both edges and Burst Lengths allow the same device to be  
useful for a variety of high bandwidth, high performance  
memory system applications.  
Serial presence detect  
Dual Rank  
* This product is under development, is not qualified or characterized and is subject to  
change without notice.  
Power supply: 2.5V 0.2V  
200 pin SO-DIMM package  
• Package height options:  
AD4: 35.05 mm (1.38”)  
BD4: 31.75 mm (1.25”)  
NOTE: Consult factory for availability of:  
• RoHS compliant products  
• Vendor source control options  
• Industrial temperature option  
OPERATING FREQUENCIES  
DDR333@CL=2.5  
166MHz  
DDR266@CL=2  
133MHz  
DDR266@CL=2.5  
133MHz  
DDR200@CL=2  
100MHz  
Clock Speed  
CL-tRCD-tRP  
2.5-3-3  
2-2-2  
2.5-3-3  
2-2-2  
January 2005  
Rev. 3  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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