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W3EG7264S202JD3C

更新时间： 2024-11-01 13:15:35

品牌	Logo	应用领域
WEDC		存储内存集成电路动态存储器双倍数据速率
页数	文件大小	规格书
11页	173K
描述
DRAM,

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中文翻译

获取价格

数据手册

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W3EG7264S202JD3C 数据手册

W3EG7264S-JD3-D3

White Electronic Designs

PRELIMINARY*

512MB – 64Mx72 DDR SDRAM UNBUFFERED

FEATURES

DESCRIPTION

The W3EG7264S is a 64Mx72 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

components. The module consists of nine 64Mx8 DDR

SDRAMs in 66 pin TSOP packages mounted on a 184

pin FR4 substrate.

ꢀ

Double-data-rate architecture

DDR200, DDR266, DDR333 and DDR400

• JEDEC design speciﬁcations

ꢀ

Bi-directional data strobes (DQS)

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input.

Auto and self refresh

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

Serial presence detect

Power supply: DDR333, 266, 200: V_CC= V_CCQ

+2.5V 0.2V; DDR400: V_CC= V_CCQ= +2.6V 0.1V

ꢀ

JEDEC standard 184 pin DIMM package

•

PCB Height: 30.48mm (1.20") Max

NOTE: Consult Factory for availability of:

* Lead-Free Products

* Vendor source control options

* Industrial Temperature option

OPERATING FREQUENCIES

DDR400 @CL=3

DDR333 @CL=2.5

166MHz

DDR266 @CL=2

133MHz

DDR266 @CL=2.5

133MHz

DDR200 @CL=2

100MHz

Clock Speed

CL-t_RCD-t_RP

200MHz

3-3-3

2.5-3-3

2-2-2

2.5-3-3

2-2-2

May 2005

Rev. 5

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...11

中文翻译

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