Datasheet > W310

W310

更新时间： 2024-11-17 23:41:31

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
24页	207K
描述
Clocks and Buffers

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中文翻译

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数据手册

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W310 数据手册

PRELIMINARY

W310

Spread Spectrum FTG for VIA K7 Chipset

Features

• Single-chip system frequency synthesizer for VIA K7

chipset

Input Address

• Pin compatible with W210, W230 and W230-03

• Programmable clock output frequency with less than

1 MHz increment

CPU_CS

CPUT0 (MHz)

PCI 0:5

(MHz)

• Integrated fail-safe Watchdog Timer for system recov-

ery

• Automatically switch to HW selected or SW pro-

grammed clock frequency when Watchdog Timer time-

out

• Capable of generate system RESET after a Watchdog

Timer time-out occurs or a change in output frequency

via SMBus interface

• Support SMBus byte read/write and block read/ write

operations to simplify system BIOS development

• Vendor ID and Revision ID support

• Programmable drive strength for CPU, SDRAM and PCI

output clocks

• Programmable output skew between CPU, PCI and

SDRAM

• Maximized EMI Suppression using Cypress’s Spread

Spectrum technology

100.0

95.0

33.3

31.7

33.3

34.0

34.6

35.3

35.6

36.0

36.3

36.6

37.0

37.3

133.3

102.0

104.0

106.0

107.0

108.0

109.0

110.0

111.0

112.0

• Available in 48-pin SSOP

Key Specifications

CPU to CPU Output Skew:...........................................175 ps

PCI to PCI Output Skew: ..............................................500 ps

V_DD: .........................................................................3.3V ±5%

SDRAMIN to SDRAM0:12 Delay:...........................3.7 ns typ.

Table 1. Mode Input Table

Mode

Pin 2

CPU_STOP#

REF0

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07258 Rev. *A

Revised December 19, 2002

12 3 4 5 6 7...24

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