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W312-02H PDF预览

W312-02H

更新时间: 2024-11-17 22:14:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体外围集成电路光电二极管时钟
页数 文件大小 规格书
21页 145K
描述
FTG for VIA K7 Series Chipset with Programmable Output Frequency

W312-02H 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.47其他特性:ALSO REQUIRES 2.5V SUPPLY
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:2.5/3.3 V主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5057 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

W312-02H 数据手册

 浏览型号W312-02H的Datasheet PDF文件第2页浏览型号W312-02H的Datasheet PDF文件第3页浏览型号W312-02H的Datasheet PDF文件第4页浏览型号W312-02H的Datasheet PDF文件第5页浏览型号W312-02H的Datasheet PDF文件第6页浏览型号W312-02H的Datasheet PDF文件第7页 
W312-02  
FTG for VIA™ K7 Series Chipset with Programmable Output Frequency  
• Low jitter and tightly controlled clock skew  
• Two pairs of differential CPU clocks  
• Eleven copies of PCI clocks  
• Three copies of 66-MHz outputs  
• Two copies of 48-MHz outputs  
• Three copies of 14.31818-MHz reference clocks  
• One RESET output for system recovery  
• Power management control support  
Features  
• Single chip FTG solution for VIA™ K7 Series chipsets  
• Programmable clock output frequency with less than  
1 MHz increment  
• Integrated fail-safe Watchdog timer for system recov-  
ery  
• Automatically switch to HW selected or SW  
programmed clock frequency when watchdog timer  
time-out  
Key Specifications  
• Capable of generate system RESET after a watchdog  
timer time-out occurs or a change in output frequency  
via SMBus interface  
CPU Outputs Cycle-to-cycle Jitter: .............................250 ps  
• Support SMBus byte read/write and block read/ write  
operations to simplify system BIOS development  
48-MHz, 3V66, PCI Outputs  
Cycle-to-cycle Jitter:....................................................500 ps  
• Vendor ID and Revision ID support  
• Programmable drive strength for PCI output clocks  
• ProgrammableoutputskewbetweenCPU,AGPandPCI  
• Maximized EMI suppression using Cypress’s Spread  
Spectrum technology  
CPU, 3V66 Output Skew:............................................200 ps  
48-MHz Output Skew: .................................................250 ps  
PCI Output Skew:........................................................500 ps  
[1]  
Block Diagram  
Pin Configuration  
VDD_REF  
VDD_REF  
GND_REF  
X1  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
REF0/FS0*  
REF1/FS1*  
REF2  
REF_STOP#*  
AGP_STOP#*  
GND_CPU  
CPUT0  
1
2
REF2  
REF1/FS1*  
X1  
X2  
3
XTAL  
OSC  
X2  
4
REF0/FS0*  
VDD_48MHz  
*FS2/48MHz  
*FS3/24_48MHz  
GND_48MHz  
*FS4/PCI_F  
*SEL24_48#/PCI0  
PCI1  
5
PLL REF FREQ  
VDD_CPU  
6
7
8
9
Divider,  
Delay,  
and  
Phase  
Control  
Logic  
CPUT0,CPUC0  
CPUT_CS,CPUC_CS  
CPUC0  
2
SDATA  
SCLK  
SMBus  
Logic  
VDD_CPU  
CPUT_CS  
CPUC_CS  
GND_CPU  
CPU_STOP#*  
PCI_STOP#*  
PD#*  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VDD_AGP  
AGP0:2  
GND_PCI  
PCI2  
3
(FS0:4)  
PCI3  
VDD_PCI  
PCI4  
VDD_PCI  
VDD_CORE  
GND_CORE  
SDATA  
SCLK  
GND_AGP  
AGP2  
AGP1  
AGP0  
VDD_AGP  
PCI0/SEL24_48#*  
PCI5  
PCI6  
PLL 1  
PCI1:8  
5
GND_PCI  
PCI7  
PD#  
CPU_STOP#  
PCI_STOP#  
AGP_STOP#  
REF_STOP#  
PCI9_E  
PCI8  
PCI9_E  
VDD_PCI  
RST#  
RST#  
VDD_48MHz  
48MHz/FS3*  
Note:  
1. Internal 100K pull-up resistors present on inputs marked with *. De-  
sign should not rely solely on internal pull-up resistor to set I/O pins  
HIGH.  
PLL2  
24_48MHz/FS4*  
/2  
SEL24_48#*  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07259 Rev. *B  
Revised December 19, 2002  

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