W312-02
FTG for VIA™ K7 Series Chipset
with Programmable Output Frequency
• Low jitter and tightly controlled clock skew
Features
• Two pairs of differential CPU clocks
• Single chip FTG solution for VIA™ K7 Series chipsets
• Eleven copies of PCI clocks
• Programmable clock output frequency with less than
1 MHz increment
• Three copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• Integrated fail-safe Watchdog timer for system
recovery
• Three copies of 14.31818-MHz reference clocks
• One RESET output for system recovery
• Power management control support
• Automatically switch to HW selected or SW
programmed clock frequency when watchdog timer
time-out
• Capable of generate system RESET after a watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
Key Specifications
CPU Outputs Cycle-to-cycle Jitter: .............................250 ps
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
48-MHz, 3V66, PCI Outputs
Cycle-to-cycle Jitter:....................................................500 ps
• Vendor ID and Revision ID support
CPU, 3V66 Output Skew:............................................200 ps
48-MHz Output Skew: .................................................250 ps
PCI Output Skew:........................................................500 ps
• Programmable drive strength for PCI output clocks
• ProgrammableoutputskewbetweenCPU,AGPandPCI
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Block Diagram
Pin Configuration[1]
VDD_REF
REF2
REF1/FS1*
REF0/FS0*
VDD_REF
GND_REF
X1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/FS0*
REF1/FS1*
REF2
REF_STOP#*
AGP_STOP#*
GND_CPU
CPUT0
1
2
3
4
5
6
7
8
X1
X2
XTAL
OSC
X2
VDD_48MHz
*FS2/48MHz
*FS3/24_48MHz
GND_48MHz
*FS4/PCI_F
*SEL24_48#/PCI0
PCI1
PLL REF FREQ
VDD_CPU
CPUT0,CPUC0
CPUT_CS,CPUC_CS
Divider,
Delay,
and
CPUC0
2
SDATA
SCLK
SMBus
Logic
VDD_CPU
CPUT_CS
CPUC_CS
GND_CPU
CPU_STOP#*
PCI_STOP#*
PD#*
VDD_CORE
GND_CORE
SDATA
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Phase
Control
Logic
VDD_AGP
AGP0:2
GND_PCI
PCI2
PCI3
VDD_PCI
PCI4
PCI5
3
(FS0:4)
VDD_PCI
PCI0/SEL24_48#*
PLL 1
PCI1:8
PCI6
5
GND_PCI
PCI7
PCI8
PCI9_E
VDD_PCI
RST#
SCLK
PD#
CPU_STOP#
PCI_STOP#
GND_AGP
AGP2
AGP1
AGP0
VDD_AGP
PCI9_E
AGP_STOP#
REF_STOP#
RST#
VDD_48MHz
48MHz/FS3*
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. De-
sign should not rely solely on internal pull-up resistor to set I/O pins
HIGH.
PLL2
24_48MHz/FS4*
/2
SEL24_48#*
Rev 1.0, November 27, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Page 1 of 19
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com