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W311H PDF预览

W311H

更新时间: 2024-11-18 03:17:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管双倍数据速率
页数 文件大小 规格书
19页 372K
描述
FTG for VIA⑩ Pro-266 DDR Chipset

W311H 技术参数

是否Rohs认证:不符合生命周期:Transferred
零件包装代码:SSOP包装说明:SSOP, SSOP48,.4
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.48Is Samacsys:N
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:15.875 mm湿度敏感等级:1
端子数量:48最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):220
电源:2.5,3.3 V主时钟/晶体标称频率:14.31818 MHz
认证状态:Not Qualified座面最大高度:2.794 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5057 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

W311H 数据手册

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W311  
FTG for VIA™ Pro-266 DDR Chipset  
• Supports Intel® Celeron® and Pentium® III class  
Features  
processor  
• Maximized EMI Suppression using Cypress’s Spread  
• Three copies of CPU output  
• Nine copies of PCI output  
• One 48-MHz output for USB  
• One 24-MHz or 48-MHz output for SIO  
• Two buffered reference outputs  
• Three copies of APIC output  
• Supports frequencies up to 200MHz  
• SMBus Interface for programming  
• Power management control inputs  
• Available in 48-pin SSOP  
Spectrum Technology  
• System frequency synthesizer for VIA Pro-2000  
• Programmable clock output frequency with less than 1  
MHz increment  
• Integrated fail-safe Watchdog Timer for system  
recovery  
• Automatically switch to HW selected or SW  
programmed clock frequency when Watchdog Timer  
time-out  
• Capable of generate system RESET after a Watchdog  
Timer time-out occurs or a change in output frequency  
via SMBus interface  
Key Specifications  
• Support SMBus byte read/write and block read/ write  
operations to simplify system BIOS development  
CPU Cycle-to-cycle Jitter: ..........................................250 ps  
CPU to CPU Output Skew...........................................175 ps  
PCI Cycle-to-cycle Jitter:.............................................500 ps  
PCI to PCI Output Skew:.............................................500 ps  
• Vendor ID and Revision ID support  
• Programmable drive strength for CPU and PCI output  
clocks  
• ProgrammableoutputskewbetweenCPU, AGPandPCI  
Block Diagram  
Pin Configuration[1]  
Note:  
1. Signals marked with * have internal pull-up resistors  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07703 Rev. **  
Revised March 14, 2005  

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