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W27E02Q-90 PDF预览

W27E02Q-90

更新时间: 2024-11-08 19:47:55
品牌 Logo 应用领域
华邦 - WINBOND 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
16页 277K
描述
EEPROM, 256KX8, 90ns, Parallel, CMOS, PDSO32, 8 X 14 MM, STSOP-32

W27E02Q-90 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP包装说明:TSOP1, TSSOP32,.56,20
针数:32Reach Compliance Code:unknown
ECCN代码:3A991.B.1.B.1HTS代码:8542.32.00.51
风险等级:5.92最长访问时间:90 ns
命令用户界面:NO数据轮询:NO
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
长度:12.4 mm内存密度:2097152 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:32
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX8
封装主体材料:PLASTIC/EPOXY封装代码:TSOP1
封装等效代码:TSSOP32,.56,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
编程电压:5 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.0001 A
子类别:EEPROMs最大压摆率:0.03 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30切换位:NO
宽度:8 mmBase Number Matches:1

W27E02Q-90 数据手册

 浏览型号W27E02Q-90的Datasheet PDF文件第2页浏览型号W27E02Q-90的Datasheet PDF文件第3页浏览型号W27E02Q-90的Datasheet PDF文件第4页浏览型号W27E02Q-90的Datasheet PDF文件第5页浏览型号W27E02Q-90的Datasheet PDF文件第6页浏览型号W27E02Q-90的Datasheet PDF文件第7页 
Preliminary W27E02  
´ 8 ELECTRICALLY ERASABLE EPROM  
256K  
1. GENERAL DESCRIPTION  
The W27E02 is a high speed, low power consumption Electrically Erasable and Programmable Read  
Only Memory organized as 262,144 ´ 8 bits. It requires only one supply in the range of 5.0V ± 10% in  
normal read mode. The W27E02 provides an electrical chip erase function.  
2. FEATURES  
· Fully static operation  
· Single power supply voltage: 5.0V ±10%  
· High speed access time: 70/90 nS (max.)  
· Read operating current: 30 mA (max.)  
· All inputs and outputs directly TTL/CMOS  
compatible  
· Three-state outputs  
· Erase/Programming operating current:  
30 mA (max.)  
· Available packages: 32-pin 600 mil DIP, 32-lead  
PLCC and 32-lead STSOP  
· Standby current: 20 mA (max.)  
· +12V erase/programming voltage  
3. PIN CONFIGURATIONS  
4. BLOCK DIAGRAM  
V
DD  
Vss  
V
PP  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
Vpp  
A16  
A15  
A12  
A7  
1
V
Q0  
.
.
DD  
#PGM  
#CE  
#
OUTPUT  
BUFFER  
A
1
7
2
#PGM  
A17  
A14  
A13  
A8  
A
1
6
A
1
2
A
1
5
V
p
p
V
D
D
P
G
M
CONTROL  
DECODER  
3
Q7  
#OE  
4
5
3
2
3
1
4
3
2
1
3
0
6
A6  
5
6
7
8
9
10  
11  
12  
13  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A13  
A8  
A7  
7
A5  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
A9  
32-pin  
PDIP  
A0  
.
A4  
8
A11  
A9  
32-lead PLCC  
9
A3  
CORE  
ARRAY  
A11  
#OE  
A10  
#CE  
Q7  
#OE  
A10  
10  
11  
12  
13  
14  
A2  
.
A1  
#CE  
Q7  
1
8
1
9
2
0
1
7
1
4
1
5
1
6
A17  
A0  
Q0  
Q6  
Q5  
Q
1
Q
2
V
s
s
Q
3
Q
4
Q
5
Q
6
Q1  
Q2  
18  
17  
15  
16  
Q4  
Q3  
Vss  
5. PIN DESCRIPTION  
SYMBOL  
A0 - A17  
Q0 - Q7  
#CE  
#OE  
#PGM  
VPP  
DESCRIPTION  
Address Inputs  
A11  
A9  
1
2
3
32  
#OE  
A10  
#CE  
Q7  
31  
30  
29  
28  
27  
26  
25  
A8  
A13  
A14  
4
5
Q6  
Q5  
Data Inputs/Outputs  
Chip Enable  
Output Enable  
Program Enable  
Program/Erase Supply Voltage  
Power Supply  
6
7
A17  
#PGM  
Q4  
Q3  
V
V
DD  
8
32-lead STSOP  
V
PP  
9
24  
23  
22  
21  
20  
19  
18  
17  
SS  
10  
A16  
A15  
Q2  
Q1  
Q0  
11  
12  
13  
14  
15  
16  
A12  
A7  
A6  
A5  
A4  
A0  
A1  
A2  
A3  
VDD  
Vss  
Ground  
NC  
No Connection  
Publication Release Date: May 30, 2002  
Revision A1  
- 1 -  

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