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W27C02P-70 PDF预览

W27C02P-70

更新时间: 2024-11-21 23:41:31
品牌 Logo 应用领域
其他 - ETC 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
16页 283K
描述
EEPROM|256KX8|CMOS|LDCC|32PIN|PLASTIC

W27C02P-70 数据手册

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W27C02  
´ 8 ELECTRICALLY ERASABLE EPROM  
256K  
GENERAL DESCRIPTION  
The W27C02 is a high speed, low power consumption Electrically Erasable and Programmable Read  
Only Memory organized as 262,144 x 8 bits. It requires only one supply in the range of 5.0V ±5% in  
normal read mode. The W27C02 provides an electrical chip erase function.  
FEATURES  
· Fully static operation  
· Single power supply voltage: 5.0V ±5%  
· High speed access time: 70 nS (max.)  
· Read operating current: 30 mA (max.)  
· All inputs and outputs directly TTL/CMOS  
compatible  
· Three-state outputs  
· Erase/Programming operating current:  
30 mA (max.)  
· Available packages: 32-pin 600 mil DIP, 32-lead  
PLCC and 32-lead STSOP  
· Standby current: 20 mA (max.)  
· +12V erase/programming voltage  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
V
DD  
Vss  
V
PP  
Q0  
.
.
#PGM  
#CE  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
V
Vpp  
A16  
A15  
A12  
A7  
1
DD  
#
OUTPUT  
BUFFER  
A
1
7
2
#PGM  
A17  
A14  
A13  
A8  
A
1
6
A
1
2
A
1
5
V
p
p
V
D
D
P
G
M
CONTROL  
DECODER  
3
Q7  
#OE  
4
5
3
2
3
1
4
3
2
1
3
0
6
A6  
5
6
7
8
9
10  
11  
12  
13  
29  
28  
27  
26  
25  
24  
23  
22  
21  
A14  
A13  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Q0  
7
A5  
A9  
A11  
A0  
.
32-pin  
PDIP  
A4  
8
A9  
32-lead PLCC  
CORE  
ARRAY  
9
A3  
A11  
#OE  
A10  
#CE  
Q7  
#OE  
A10  
10  
11  
12  
13  
14  
A2  
.
A1  
#CE  
Q7  
1
8
1
9
2
0
1
7
1
4
1
5
1
6
A17  
A0  
Q0  
Q6  
Q5  
Q4  
Q3  
Q
1
Q
2
V
s
s
Q
3
Q
4
Q
5
Q
6
Q1  
Q2  
18  
17  
15  
16  
Vss  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
Data Inputs/Outputs  
A11  
A9  
1
2
3
32  
31  
30  
29  
28  
27  
26  
25  
#OE  
A10  
#CE  
Q7  
Q6  
Q5  
A8  
A13  
A14  
A1 - A17  
Q0 - Q7  
#CE  
#OE  
#PGM  
VPP  
4
5
6
7
A17  
#PGM  
VDD  
Q4  
Q3  
8
32-lead STSOP  
VPP  
V
SS  
9
24  
23  
22  
21  
20  
19  
18  
17  
Chip Enable  
10  
A16  
A15  
Q2  
Q1  
Q0  
A0  
A1  
A2  
A3  
11  
12  
13  
14  
15  
16  
Output Enable  
Program Enable  
Program/Erase Supply Voltage  
Power Supply  
A12  
A7  
A6  
A5  
A4  
VDD  
Vss  
Ground  
NC  
No Connection  
Publication Release Date: April 11, 2002  
Revision A2  
- 1 -  

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