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W27C512-45Z PDF预览

W27C512-45Z

更新时间: 2024-11-08 12:59:03
品牌 Logo 应用领域
华邦 - WINBOND 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
15页 162K
描述
EEPROM, 64KX8, 45ns, Parallel, CMOS, PDIP28, 0.600 INCH, LEAD FREE, PLASTIC, DIP-28

W27C512-45Z 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.600 INCH, LEAD FREE, PLASTIC, DIP-28
针数:28Reach Compliance Code:compliant
ECCN代码:3A991.B.1.B.2HTS代码:8542.32.00.51
风险等级:5.8最长访问时间:45 ns
JESD-30 代码:R-PDIP-T28长度:37.08 mm
内存密度:524288 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:28字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX8封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED编程电压:12 V
认证状态:Not Qualified座面最大高度:5.33 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:15.24 mmBase Number Matches:1

W27C512-45Z 数据手册

 浏览型号W27C512-45Z的Datasheet PDF文件第2页浏览型号W27C512-45Z的Datasheet PDF文件第3页浏览型号W27C512-45Z的Datasheet PDF文件第4页浏览型号W27C512-45Z的Datasheet PDF文件第5页浏览型号W27C512-45Z的Datasheet PDF文件第6页浏览型号W27C512-45Z的Datasheet PDF文件第7页 
W27C512  
64K ´ 8 ELECTRICALLY ERASABLE EPROM  
GENERAL DESCRIPTION  
The W27C512 is a high speed, low power Electrically Erasable and Programmable Read Only  
´
Memory organized as 65536 8 bits that operates on a single 5 volt power supply. The W27C512  
provides an electrical chip erase function.  
FEATURES  
· High speed access time:  
45/70/90/120 nS (max.)  
· +14V erase/+12V programming voltage  
· Fully static operation  
· Read operating current: 30 mA (max.)  
· All inputs and outputs directly TTL/CMOS  
· Erase/Programming operating current  
compatible  
30 mA (max.)  
· Three-state outputs  
· Standby current: 1 mA (max.)  
· Single 5V power supply  
· Available packages: 28-pin 600 mil DIP, 330 mil  
32-pin PLCC  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
Q0  
.
.
CE  
OUTPUT  
BUFFER  
V
CC  
1
A15  
A12  
A7  
CONTROL  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
2
A14  
A13  
A8  
OE/V  
PP  
Q7  
3
4
A6  
5
A9  
A5  
A4  
6
A11  
28-pin  
DIP  
A0  
.
7
A3  
OE/Vpp  
A10  
CORE  
8
A2  
DECODER  
ARRAY  
.
9
A1  
CE  
Q7  
10  
11  
12  
13  
14  
A0  
A15  
Q6  
Q5  
Q4  
Q3  
Q0  
Q1  
Q2  
GND  
V
CC  
GND  
A
A
V
C
C
A
1
4
A
1
3
A 1 1 N  
PIN DESCRIPTION  
7
2 5 C  
SYMBOL  
DESCRIPTION  
3
2
3
1
4
3 2 1  
3
0
29  
28  
27  
26  
25  
24  
23  
A8  
A9  
A11  
NC  
A6  
5
6
7
8
9
10  
11  
12  
13  
Address Inputs  
-
A0 A15  
A5  
A4  
A3  
A2  
A1  
A0  
NC  
Q0  
Data Inputs/Outputs  
Chip Enable  
-
Q0 Q7  
32-pin  
PLCC  
OE/Vpp  
A10  
CE  
CE  
Q7  
Q6  
22  
21  
Output Enable, Program/Erase  
Supply Voltage  
1
1
8
1
9
2
0
PP  
OE  
1
4
1
5
1
6
/V  
7
CC  
V
Power Supply  
Ground  
Q
1
Q
2
Q
4
G
N
D
Q
3
Q
5
N
C
GND  
NC  
No Connection  
Publication Release Date: November 1999  
Revision A4  
- 1 -  

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