Preliminary W27E01
´ 8 ELECTRICALLY ERASABLE EPROM
128K
1. GENERAL DESCRIPTION
The W27E01 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 131,072 ´ 8 bits. It requires only one supply in the range of 5.0V ±10% in
normal read mode. The W27E01 provides an electrical chip erase function.
2. FEATURES
· Single power supply voltage:
5.0V ±10%
· +12V erase/programming voltage
· Fully static operation
· All inputs and outputs directly TTL/CMOS
· High speed access time:
compatible
70/90 nS (max.)
· Three-state outputs
· Read operating current: 30 mA (max.)
· Erase/Programming operating current:
· Available packages: 32-pin 600 mil DIP, 32-lead
30 mA (max.)
PLCC and 32-lead STSOP
· Standby current: 20 mA (max.)
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
V
DD
Vss
V
PP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
Vpp
A16
A15
A12
A7
1
V
DD
Q0
.
.
#PGM
#CE
#
2
#PGM
NC
A
1
6
OUTPUT
BUFFER
A
1
2
A
1
5
V
p
p
V
D
D
P
G
M
CONTROL
DECODER
N
C
3
Q7
#OE
4
A14
A13
A8
5
3
2
3
1
4
3
2
1
3
0
6
A6
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A14
A13
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q0
7
A5
A9
32-pin
PDIP
8
A11
A4
A0
.
A9
32-lead PLCC
9
A3
A11
#OE
A10
#CE
Q7
#OE
A10
CORE
ARRAY
10
11
12
13
14
A2
.
A1
#CE
Q7
1
8
1
9
2
0
1
7
1
4
1
5
1
6
A0
A16
Q0
Q6
Q5
Q
1
Q
2
V
s
s
Q
3
Q
4
Q
5
Q
6
Q1
Q2
18
17
15
16
Q4
Q3
Vss
5. PIN DESCRIPTION
SYMBOL
A0 - A16
Q0 - Q7
#CE
#OE
#PGM
VPP
DESCRIPTION
Address Inputs
A11
A9
1
2
3
32
#OE
A10
#CE
Q7
Q6
Q5
31
30
29
28
27
26
25
A8
A13
4
5
A14
NC
6
7
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
#PGM
Q4
Q3
V
DD
V
PP
8
32-lead STSOP
V
9
24
23
22
21
20
19
18
17
SS
10
Q2
Q1
Q0
A0
A1
A2
A3
A16
A15
11
12
13
14
15
16
A12
A7
A6
A5
A4
VDD
Vss
Ground
NC
No Connection
Publication Release Date: May 30, 2002
Revision A1
- 1 -