W25P022AD-6

更新时间： 2024-11-14 22:11:27

品牌	Logo	应用领域
华邦 - WINBOND		/
页数	文件大小	规格书
17页	310K
描述
64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

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W25P022AD-6 数据手册

W25P022A

64K ´ 32 BURST PIPELINED HIGH-SPEED

CMOS STATIC RAM

GENERAL DESCRIPTION

The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM

organized as 65,536 ´ 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst

address counter supports both Pentiumä burst mode and linear burst mode. The mode to be

executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by

the FT pin. A snooze mode reduces power dissipation.

The W25P022A supports both 2T/2T mode and 2T/1T mode, which can be selected by pin 42. The

default mode is 2T/1T, with pin 42 low. To switch to 2T/2T mode, bias pin 42 to VDDQ. The state of

pin 42 should not be changed after power up. The 2T/2T mode will sustain one cycle of valid data

output in a burst read cycle when the device is deselected by CE2/CE3 . This mode supports 3-1-1-1-

1-1-1-1 in a two-bank, back-to-back burst read cycle. On the other hand, the 2T/1T mode disables

data output within one cycle in a burst read cycle when the device is deselected by CE2/CE3 . In this

mode, the device supports only 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.

FEATURES

· Synchronous operation

· High-speed access time: 6/7 nS (max.)

· Single +3.3V power supply

· Individual byte write capability

· 3.3V LVTTL compatible I/O

· Clock-controlled and registered input

· Asynchronous output enable

· Pipelined/non-pipelined data output capability

· Supports snooze mode (low-power state)

· Internal burst counter supports Intel burst mode

& linear burst mode

· Supports both 2T/2T & 2T/1T mode

· Packaged in 100-pin QFP or TQFP

BLOCK DIAGRAM

INPUT

A(15:0)

64K X 32

CORE

ARRAY

CLK

CE(3:1)

BWE

CONTROL

LOGIC

BW(4:1)

DATA I/O

I/O(32:1)

REGISTE

ADSC

ADSP

ADV

LBO

Publication Release Date: September 1996

- 1 -

Revision A1

12 3 4 5 6 7...17

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