5秒后页面跳转
W19B320ATT7M PDF预览

W19B320ATT7M

更新时间: 2024-10-29 06:21:31
品牌 Logo 应用领域
华邦 - WINBOND 光电二极管
页数 文件大小 规格书
53页 479K
描述
Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48

W19B320ATT7M 数据手册

 浏览型号W19B320ATT7M的Datasheet PDF文件第4页浏览型号W19B320ATT7M的Datasheet PDF文件第5页浏览型号W19B320ATT7M的Datasheet PDF文件第6页浏览型号W19B320ATT7M的Datasheet PDF文件第8页浏览型号W19B320ATT7M的Datasheet PDF文件第9页浏览型号W19B320ATT7M的Datasheet PDF文件第10页 
W19B320AT/B  
6. FUNCTIONAL DESCRIPTION  
6.1 Device Bus Operation  
6.1.1 Word/Byte Configuration  
The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration.  
When the #BYTE pin is ‘1’, the device is in word configuration; DQ0 -DQ15 are active and controlled  
by #CE and #OE.  
When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active  
and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is  
used as an input for the LSB (A-1) address function.  
6.1.2 Reading Array Data  
To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power  
control and used to select the device. #OE is the output control and gates array data to the output  
pins. #WE should stay at VIH. The #BYTE pin determines the device outputs array data whether in  
words or bytes.  
The internal state machine is set for reading array data when device power-up, or after hardware  
reset. This ensures that no excess modification of the memory content occurs during the power  
transition. In this mode there is no command necessary to obtain array data. Standard microprocessor  
read cycles that assert valid addresses on the device address inputs produce valid data on the device  
data outputs. Each bank remains enabled for read access until the command register contents are  
changed.  
6.1.3 Writing Commands/Command Sequences  
In writhing a command or command sequence (which includes programming data to the device and  
erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH.  
For program operations, the #BYTE pin determines the device accepts program data whether in bytes  
or in words. Refer to “Word/Byte Configuration” for more information.  
The Unlock Bypass mode of device is to facilitate a faster programming. When a bank enters the  
Unlock Bypass mode, only two write cycles are required to program a word or byte. Please refer to  
"Word/Byte Configuration” section for details on programming data to the device using both standard  
and Unlock Bypass command sequences.  
The erase operation can erase a sector, multiple sectors, even the entire device. The device address  
space is divided into four banks: Bank 1and Bank 4 contains the boot/parameter sectors; while Bank 2  
and Bank 3 contain the larger sectors of uniform size. The “bank address” is the address bits required  
to solely select a bank; while the “sector address” is the address bits required to solely select a sector.  
Publication Release Date: December 27, 2005  
- 7 -  
Revision A4  
 

与W19B320ATT7M相关器件

型号 品牌 获取价格 描述 数据表
W19B320ATT8M WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48
W19B320ATT9G WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, TSOP-48
W19B320ATT9H WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48
W19B320ATT9M WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48
W19B320ATTAG WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, TSOP-48
W19B320ATTAH WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48
W19B320ATTAM WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, LEAD FREE, TSOP-48
W19B320ATTBG WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, TSOP-48
W19B320ATTBL WINBOND

获取价格

Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, TSOP-48
W19B320B WINBOND

获取价格

32Mbit, 2.7~3.6-volt single bank CMOS flash memory