W124
IOAPIC Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.8/100MHz
Symbol Parameter
Min
Typ
Max
Unit
Test Condition/Comments
f
t
Frequency, Actual
14.31818
MHz
V/ns
Frequency generated by crystal oscillator.
Measured from 0.4V to 2.0V.
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
1
1
4
4
R
F
t
t
t
V/ns
%
Measured from 2.0V to 0.4V.
45
55
500
Measured on rising and falling edge at 1.25V.
D
A
Jitter, Absolute
ps
Measured on rising edge at 1.25V. Maximum
deviation of clock period.
f
Frequency Stabilization from
Power-up (cold start)
3
ms
Assumes full supply voltage reached within 1ms
from power-up. Short cycles exist prior to
frequency stabilization.
ST
Z
AC Output Impedance
15
ohm
Average value during switching transition. Used
for determining series termination value.
o
REF2X Clock Output (Lump Capacitance Test Load = 20pF)
CPU =66.8/100MHz
Symbol Parameter
Min
Typ
Max
Unit
Test Condition/Comments
f
t
Frequency, Actual
14.318
MHz
V/ns
Frequency generated by crystal oscillator.
Measured from 0.4V to 2.4V.
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
R
t
t
f
V/ns
%
Measured from 2.4V to 0.4V.
F
55
3
Measured on rising and falling edge at 1.5V.
D
Frequency Stabilization from
Power-up (cold start)
ms
Assumes full supply voltage reached within 1ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
ST
Z
AC Output Impedance
20
ohm
Average value during switching transition. Used for
determining series termination value.
o
48MHz and 24MHz Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.8/100MHz
Symbol Parameter
Min
Typ
Max
Unit
Test Condition/Comments
f
Frequency, Actual
48.008
24.004
MHz
Determined by PLL divider ratio (see m/nbelow).
f
Deviation from 48MHz
+167
ppm
(48.008 – 48)/48
D
m/n
PLL Ratio
57/17, 57/34
(14.31818MHz x 57/17 = 48.008MHz)
Measured from 0.4V to 2.4V.
t
Output Rise Edge Rate
0.5
0.5
45
2
2
V/ns
V/ns
%
R
t
t
f
Output Fall Edge Rate
Duty Cycle
Measured from 2.4V to 0.4V.
F
55
3
Measured on rising and falling edge at 1.5V.
D
Frequency Stabilization from
Power-up (cold start)
ms
Assumes full supply voltage reached within 1ms
from power-up. Short cycles exist prior to frequency
stabilization.
ST
Z
AC Output Impedance
25
ohm
Average value during switching transition. Used for
determining series termination value.
o
Page 12
100MHz Spread Spectrum Motherboard Frequency Generator
Revision 1.0