W124
AC Electrical Characteristics:
T
= 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; f
= 14.31818MHz
XTL
A
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20pF)
CPU = 66.8MHz
CPU = 100MHz
Symbol Parameter
Min
Typ
Max
Min
Typ
Max
Unit Test Condition/Comments
t
t
t
t
t
t
t
Period
15
5.2
5.0
1
15.5
10
3.0
2.8
1
10.5
ns
ns
ns
Measured on rising edge at 1.25.
Duration of clock cycle above 2.0V.
Duration of clock cycle below 0.4V.
P
High Time
H
L
Low Time
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
4
4
V/ns Measured from 0.4V to 2.0V.
V/ns Measured from 2.0V to 0.4V.
R
F
1
1
45
55
200
45
55
200
%
Measured on rising and falling edge at 1.25V.
D
JC
Jitter, Cycle-to-Cycle
ps
Measured on rising edge at 1.25V. Maximum
difference of cycle time between two adjacent
cycles.
t
f
Output Skew
175
3
175
3
ps
Measured on rising edge at 1.25V.
SK
ST
Frequency Stabilization
from Power-up (cold start)
ms
Assumes full supply voltage reached within
1ms from power-up. Short cycles exist prior to
frequency stabilization.
Z
AC Output Impedance
20
20
Average value during switching transition.
Used for determining series termination value.
ohm
o
PCI Clock Outputs, PCI1:6 and PCI_F(Lump Capacitance Test Load = 30pF)
CPU = 66.8/100MHz
Symbol Parameter
Min
30
Typ
Max
Unit
ns
Test Condition/Comments
t
t
t
t
t
t
t
Period
Measured on rising edge at 1.5V.
Duration of clock cycle above 2.4V.
Duration of clock cycle below 0.4V.
Measured from 0.4V to 2.4V.
P
High Time
12.0
12.0
1
ns
H
L
Low Time
ns
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
R
F
1
Measured from 2.4V to 0.4V.
45
55
250
Measured on rising and falling edge at 1.5V.
D
JC
Jitter, Cycle-to-Cycle
ps
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
t
t
Output Skew
500
4.0
ps
ns
Measured on rising edge at 1.5V.
SK
O
CPU to PCI Clock Offset
1.5
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
f
Frequency Stabilization from
Power-up (cold start)
3
ms
Assumes full supply voltage reached within 1ms
from power-up. Short cycles exist prior to
frequency stabilization.
ST
Z
AC Output Impedance
15
ohm
Average value during switching transition. Used
for determining series termination value.
o
100MHz Spread Spectrum Motherboard Frequency Generator
Revision 1.0
Page 11