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W124GT

更新时间: 2024-01-01 22:57:05
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
13页 123K
描述
Processor Specific Clock Generator, 48MHz, CMOS, PDSO28, 0.300 INCH, SOIC-28

W124GT 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.78
其他特性:ALSO OPERATES AT 2.5 V NOMINAL SUPPLYJESD-30 代码:R-PDSO-G28
长度:10.34 mm端子数量:28
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:48 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH主时钟/晶体标称频率:100 MHz
认证状态:Not Qualified座面最大高度:2.64 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.52 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

W124GT 数据手册

 浏览型号W124GT的Datasheet PDF文件第4页浏览型号W124GT的Datasheet PDF文件第5页浏览型号W124GT的Datasheet PDF文件第6页浏览型号W124GT的Datasheet PDF文件第8页浏览型号W124GT的Datasheet PDF文件第9页浏览型号W124GT的Datasheet PDF文件第10页 
W124  
Writing Data Bytes  
Each bit in the data bytes control a particular device function  
except for the "reserved" bits which must be written as a logic  
0. Bits are written MSB (most significant bit) first, which is bit  
7. Table 5 gives the bit formats for registers located in Data  
Bytes 3-6.  
Table 6 details additional frequency selections that are avail-  
able through the serial data interface.  
Table 7 details the select functions for Byte 3, bits 1 and 0.  
Table 5 Data Bytes 3-6 Serial Configuration Map  
Affected Pin  
Bit Control  
Bit(s)  
Pin No.  
Pin Name  
Control Function  
0
1
Default  
Data Byte 3  
7
6
5
4
3
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
(Reserved)  
--  
--  
0
0
0
0
0
SEL_2  
Refer to Table 6  
Refer to Table 6  
Refer to Table 6  
SEL_1  
SEL_0  
BYT3 or SEL Pin  
Frequency Controlled  
by external SEL100/  
66# pin  
Frequency Controlled  
by BYT3 SEL (2:0)  
2
--  
--  
--  
--  
(Reserved)  
--  
--  
0
1-0  
Bit 1  
Bit 0  
Function (See Table 7 for function details)  
00  
0
0
1
1
0
1
0
1
Normal Operation  
Test Mode  
Spread Spectrum on ± 0.5% Modulation  
All Outputs Tristated  
Data Byte 4  
7
6
5
4
3
2
1
0
--  
14  
--  
--  
(Reserved)  
--  
--  
0
1
0
0
0
1
0
1
24/48MHz  
Clock output disable  
(Reserved)  
Low  
--  
Active  
--  
--  
--  
--  
--  
(Reserved)  
--  
--  
--  
(Reserved)  
--  
--  
21  
--  
CPU1  
--  
Clock Output Disable  
(Reserved)  
Low  
--  
Active  
--  
22  
CPU0  
Clock Output Disable  
Low  
Active  
Data Byte 5  
7
6
5
4
3
2
1
0
4
11  
10  
-
PCI_F  
PCI6  
PCI5  
--  
Clock Output Disable  
Clock Output Disable  
Clock Output Disable  
(Reserved)  
Low  
Low  
Low  
--  
Active  
Active  
Active  
--  
1
1
1
0
1
1
1
1
8
PCI4  
PCI3  
PCI2  
PCI1  
Clock Output Disable  
Clock Output Disable  
Clock Output Disable  
Clock Output Disable  
Low  
Low  
Low  
Low  
Active  
Active  
Active  
Active  
7
6
5
Data Byte 6  
7
6
5
4
3
2
1
0
--  
--  
--  
(Reserved)  
--  
--  
--  
--  
0
--  
IOAPIC  
--  
(Reserved)  
0
24  
--  
Clock Output Disable  
(Reserved)  
Low  
--  
Active  
--  
1
0
--  
--  
(Reserved)  
--  
--  
0
--  
--  
(Reserved)  
--  
--  
0
27  
27  
REF2X  
REF2X  
Clock Output Disable  
Clock Output Disable  
Low  
Low  
Active  
Active  
1 (Note 2)  
1 (Note 2)  
100MHz Spread Spectrum Motherboard Frequency Generator  
Revision 1.0  
Page 7  

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