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W124GT PDF预览

W124GT

更新时间: 2024-10-28 20:10:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
13页 123K
描述
Processor Specific Clock Generator, 48MHz, CMOS, PDSO28, 0.300 INCH, SOIC-28

W124GT 技术参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.78
其他特性:ALSO OPERATES AT 2.5 V NOMINAL SUPPLYJESD-30 代码:R-PDSO-G28
长度:10.34 mm端子数量:28
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:48 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH主时钟/晶体标称频率:100 MHz
认证状态:Not Qualified座面最大高度:2.64 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.52 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

W124GT 数据手册

 浏览型号W124GT的Datasheet PDF文件第2页浏览型号W124GT的Datasheet PDF文件第3页浏览型号W124GT的Datasheet PDF文件第4页浏览型号W124GT的Datasheet PDF文件第5页浏览型号W124GT的Datasheet PDF文件第6页浏览型号W124GT的Datasheet PDF文件第7页 
W124  
100MHz Spread Spectrum Motherboard Frequency Generator  
• For 3 DIMM designs, see also the W40S11-23 buffer chip,  
Features  
• Maximized EMI suppression using IC WORKS’ Spread  
Spectrum Technology  
• Reduces measured EMI by as much as 10dB  
• I2C programmable  
for 4 DIMM designs see the W40S12-24 or W40S01-04  
Key Specifications  
Supply Voltages:  
VDDQ3 = 3.3V±5%  
VDDQ2 = 2.5V±5%  
• Two skew-controlled copies of CPU output  
• Seven copies of PCI output (synchronous w/CPU output)  
• One copy of 14.31818 MHz IOAPIC output  
• One copy of 48MHz USB output  
CPU Cycle to Cycle Jitter:  
CPU, PCI Edge Rate:  
CPU0:1 Skew:  
200ps  
³ 1V/ns  
175ps  
• Selectable 24/48MHz output is determined by resistor  
straps on power up  
• One high drive output buffer that produces a copy of the  
14.318MHz reference  
PCI_F, PCI1:6 Skew:  
CPU to PCI Skew:  
Logic inputs and REF2X/SEL48# have 250Kohm pull-up  
resistors, except SEL100/66#  
500ps  
1.5 - 4.0ns (CPU Leads)  
• Programmable to 133, 124, 112, 103, 100 MHz and below  
Figure 1 Block Diagram  
Table 1 Pin Selectable Frequency  
VDDQ3  
SEL100/66#  
CPU(0:1)  
PCI  
REF2X/SEL48#  
1
0
100MHz  
66.8MHz  
33.3MHz  
33.4MHz  
X1  
X2  
XTAL  
OSC  
VDDQ2  
IOAPIC  
PLL Ref Freq  
Figure 2 Pin Diagram  
X1  
X2  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
GND  
2
REF2X/SEL48#  
VDDQ3  
VDDQ2  
IOAPIC  
VDDQ2  
CPU0  
GND  
3
PCI_F  
PCI1  
4
5
PCI2  
6
VDDQ2  
CPU0  
CPU1  
PCI3  
7
PCI4  
8
CPU1  
VDDQ3  
PCI5  
9
VDDQ3  
GND  
10  
11  
12  
13  
14  
SDATA  
PCI6  
SEL100/66#  
VDDQ3  
48MHz  
24/48MHz  
SCLOCK  
SEL100/66#  
PLL 1  
÷2/÷3  
GND  
VDDQ3  
PCI_F  
PCI1  
PCI2  
Table 2 Order Information  
PCI3  
Part Number  
Package  
PCI4  
PCI5  
PCI6  
W124  
G = SOIC (300 mils)  
I2C  
LOGIC  
SDATA  
SCLOCK  
VDDQ3  
48MHz  
PLL2  
÷1/÷2  
24/48MHz  
September 1998  
Revision 1.0  
IC WORKS · 101 Nicholson Lane · San Jose, CA 95134-1359 · (408) 922-0202  

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