Datasheet > W124GT

W124GT

更新时间： 2024-02-29 08:26:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
13页	123K
描述
Processor Specific Clock Generator, 48MHz, CMOS, PDSO28, 0.300 INCH, SOIC-28

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W124GT 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.78
其他特性：	ALSO OPERATES AT 2.5 V NOMINAL SUPPLY	JESD-30 代码：	R-PDSO-G28
长度：	10.34 mm	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	48 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	主时钟/晶体标称频率：	100 MHz
认证状态：	Not Qualified	座面最大高度：	2.64 mm
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	7.52 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

W124GT 数据手册

W124

Overview

The W124 a motherboard clock synthesizer, can provide

either a 2.5V or 3.3V CPU clock swing making it suitable for a

variety of CPU options. A fixed 48MHz clock is provided for

other system functions. The device W124 supports spread

spectrum clocking for reduced EMI.

clock load to either a logic high or low state. At the end of the

2ms period, the established logic "0" or "1" condition of the l/

O pin is then latched. Next the output buffer is enabled which

converts the l/O pin into an operating clock output. The 2ms

timer is started when VDD reaches 2.0V. The input bit can

only be re-set by turning VDD off and then back on again.

Functional Description

It should be noted that the strapping resistor has no signifi-

cant effect on clock output signal integrity. The drive imped-

ance of clock output is 25 ohms (nominal) which is minimally

affected by the 10 kohm strap to ground or VDD. As with the

series termination resistor, the output strapping resistor

should be placed as close to the l/O pin as possible in order

to keep the interconnecting trace short. The trace from the

resistor to ground or VDD should be kept less than two

inches in length to prevent system noise coupling during

input logic sampling.

I/O Pin Operation

Pin 27 is a dual purpose l/O pin. Upon power up this pin acts

as a logic input, allowing the determination of assigned

device functions. A short time after power up, the logic state

of the pin is latched and the pin becomes a clock output. This

feature reduces device pin count by combining clock outputs

with input select pins.

An external 10 kohm "strapping" resistor is connected

between the l/O pin and ground or VDD. Connection to

ground sets a latch to "0", connection to VDD sets a latch to

"1’. Figure 3 and Figure 4 show two suggested methods for

strapping resistor connections.

When the clock output is enabled following the 2ms input

period, a 14.318MHz output frequency is delivered on the

pin, assuming that VDD has stabilized. If VDD has not yet

reached full value, output frequency initially may be below

target but will increase to target once VDD voltage has stabi-

lized. In either case, a short output clock cycle may be pro-

duced from the CPU clock outputs when the outputs are

enabled.

Upon W124 power up, the first 2ms of operation is used for

input logic selection. During this period, the Reference clock

output buffer is tristated, allowing the output strapping resis-

tor on the l/O pin to pull the pin and its associated capacitive

Figure 3 Input Logic Selection Through Resistor Load Option

VDD

OutputStrappingResistor

Series Termination Resistor

10kW

(LoadOption1)

Clock Load

W124

Output

Buffer

Power-on

Reset

Timer

Hold

Output

Low

OutputTristate

10kW

(LoadOption0)

Data

Latch

Figure 4 Input Logic Selection Through Jumper Option

Jumper Options

OutputStrappingResistor

Series Termination Resistor

VDD

10k W

W124

Clock Load

Output

Buffer

Power-on

Reset

Timer

ResistorValueR

Hold

Output

Low

OutputTristate

Data

Latch

100MHz Spread Spectrum Motherboard Frequency Generator

Revision 1.0

Page 3

1 234 5 6 7...13

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