Datasheet > VSC8117

VSC8117

更新时间： 2024-02-16 19:42:57

品牌	Logo	应用领域
VITESSE		时钟发生器异步传输模式 ATM
页数	文件大小	规格书
22页	408K
描述
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

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技术参数
数据手册

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VSC8117 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.83

VSC8117 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

VSC8117

Figure 3: Facility Loopback Data Path

1:8

Serial to

Parallel

RXOUT[7:0]

CRU

RXDATAIN

Recovered

Clock

Divide-by-8

RXLSCKOUT

TXIN[7:0]

RXCLKIN

8:1

TXDATAOUT

Parallel to

Serial

PLL

FACLOOP

Equipment Loopback

The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is

set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-

lel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the

receiver section and presented to the low speed parallel outputs (RXOUT[7:0]). See Figure 4. The internally

generated 155/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equip-

ment Loopback mode the transmit data (TXIN[7:0]) is serialized by the on-chip CMU and presented at the high

speed output (TXDATAOUT).

CRU Equipment Loopback

Exactly the same as equipment loopback, the point where the transmit data is looped back is moved all the

way back to the high speed I/O. When the CRUEQLP signal is set high, transmit data is looped back to the

CRU, replacing RXDATAIN±

Figure 4: Equipment Loopback Data Path

1:8

RXOUT[7:0]

RXDATAIN

EQULOOP

Serial to

Parallel

RXLSCKOUT

TXIN[7:0]

÷ 8

TXDATAOUT

8:1

Parallel to

Serial

PLL

÷ 8

TXLSCKOUT

G52221-0, Rev. 4.1

1/8/00

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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