Datasheet > VSC8117

VSC8117

更新时间： 2024-01-17 07:46:24

品牌	Logo	应用领域
VITESSE		时钟发生器异步传输模式 ATM
页数	文件大小	规格书
22页	408K
描述
ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

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技术参数
数据手册

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VSC8117 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.83

VSC8117 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

VSC8117

CRU clock and data signals. (In this mode the VSC8117 operates just like the VSC8111 and VSC8116). The

receive section also contains a SONET/SDH frame detector circuit which is used to provide frame pluses during

the A1, A2 boundary in the serial to parallel converter. This only occurs when OOF is high. Both internal and

external LOS functions are supported. The high speed serial signals can be made PECL compatible or LVPECL

compatible by setting the proper voltage on the V

supply pins

DDP

VSC8117 Block Diagram

OOF

EQULOOP

DSBLCRU

FRAMER

1:8

DEMUX

RXOUT[7:0]

RXDATAIN+/-

CRUEQLP

REC-DATA

REC-CLK

CRU

Divide-by-8

RXLSCKOUT

RXCLKIN+/-

LOSPECL

LOSDETEN_

losdet

STS12

CRUREFCLK

CRUREFSEL

REFCLKP+/-

REFCLK

CMU

CMUFREQSEL

LOOPTIM0

TXDATAOUT+/-

FACLOOP

8:1

TXIN[7:0]

MUX

Divide-by-8

TXLSCKOUT

Page 2

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52221-0, Rev 4.1

1/8/00

123 4 5 6 7...22

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VSC8120	VITESSE	Clock Recovery Circuit, 1-Func, GAAS, PQFP64, 10 X 10 MM, PLASTIC, QFP-64	获取价格