VITESSE
SEMICONDUCTOR CORPORATION
Product Summary
10Mb/s to 2.7Gb/s Rate Agile,
Adaptive Clock and Data Recovery
VSC8123
Features
• Continuous NRZ Frequency Coverage from
• User-Definable Control Algorithms for
10Mb/s to 2.7Gb/s data rates
Acquisition, Tracking, and Error Profiling
• Programmable Acquisition and Tuning of Frequency,
Phase and Voltage—No Reference Clock Required
• Integrated High-Gain AGC Front End with
Offset Correction and On-Die Termination
• Built-In Bit Level Error Rate Monitoring Operates
Independently of In-Service Data Channel
• Secondary High-Level Input for Backup Data
Input or hint/LOS Clock
• 80-Pin PQFP Package
General Description
The VSC8123 is a universal clock and data recovery system designed for a broad range of system applica-
tions. The integrated frequency synthesizer provides continuous coverage from 10Mb/s to OC-48+FEC data
rates with SONET quality output. In addition to its broadband capability, the VSC8123 is designed for the most
demanding applications, where signal integrity is low and the absolute maximum voltage and timing margin is
required. The VSC8123 offers signal acquisition capabilities far beyond what conventional CDRs offer, in a
highly monolithic form.
In addition to the broadband synthesizer capability, the VSC8123 also has the ability to dynamically modify
its acquisition point in both voltage and phase. This enables the VSC8123 to acquire data in the presence of sig-
nificant symmetry distortion or “bad spots” in the data eye. Integrated voltage and phase adjustment is provided
to offset the sampling point over the entire voltage and phase range of the input data eye. Additional circuitry is
provided to measure relative bit-error rates without affecting the integrity of the active data stream. Using an
external controller, the VSC8123 can acquire frequency, scan the incoming data eye and automatically set its
position to optimize margin in both voltage and phase. This optimization can be one-time on power-up, or set to
continuously repeat without taking the data stream off-line—no errors will be introduced into the output data
stream as the chip tracks the center of the data eye.
Through the controller interface, the VSC8123 can provide telemetry on the condition of the incoming data
eye and the quality of the acquisition without taking the data off-line, enabling eye profiling, Q-testing, signal
strength measurements, and bit-level error detection/prediction—all non-invasively.
System Block Diagram
Transceiver or
TIA
CDR
Demultiplexer
VSC8145
VSC8141
VSC7969
VSC8123
Controller
System Interface
Notice
Vitesse Semiconductor Corporation (“Vitesse”) provides this document for informational purposes only. This document contains pre-production information
about Vitesse products in their concept, development and/or testing phase. All information in this document, including descriptions of features, functions,
performance, technical specifications and availability, is subject to change without notice at any time. Nothing contained in this document shall be construed
as extending any warranty or promise, express or implied, that any Vitesse product will be available as described or will be suitable for or will accomplish
any particular task.
Vitesse Semiconductor Corporation’s products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such appli-
cations without written consent is prohibited.
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
PS120500
Page 1
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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