Datasheet > VSC8123RB

VSC8123RB

更新时间： 2024-01-08 19:20:41

品牌	Logo	应用领域
美高森美 - MICROSEMI		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
8页	102K
描述
Clock Recovery Circuit, 1-Func, PQFP80, PLASTIC, QFP-80

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技术参数
数据手册

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VSC8123RB 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	QFP,	针数：	80
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PQFP-G80
长度：	14 mm	功能数量：	1
端子数量：	80	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	认证状态：	Not Qualified
座面最大高度：	2.35 mm	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm

VSC8123RB 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

10 Mb/s to 2.7 Gb/s

Adaptive Clock and Data Recovery

VSC8123

Features

• User definable control algorithms for acqui-

sition, tracking, and error profiling

• Continous frequency coverage from 10 Mbits/sec to

2.7 Gbits/sec data rates

• Integrated high-gain AGC front end with

offset correction and on-die termination

• Programmable acquisition and tuning of frequency,

phase and voltage -- no reference clock required

• Secondary high-level input for backup data

input or hint/LOS clock

• Built-in bit level error rate monitoring operates

independently of in-service data channel

Typical System Block Diagram

TIA

CDR

Demultiplexer

VSC8140/

VSC8164

VSC7948

VSC8123

System interface

Controller

General Description

The VSC8123 is a universal clock and data recovery system designed for a broad range of system applica-

tions. The integrated frequency synthesizer provides continuous coverage from 10 Mbits/sec to OC-48+FEC

data rates with SONET quality output. In addition to its broadband capability, the VSC8123 is designed for the

most demanding applications, where signal integrity is low and the absolute maximum voltage and timing mar-

gin is required. The VSC8123 offers signal acquisition capabilities far beyond what conventional CDRs offer, in

a highly monolithic form.

In addition to the broadband synthesizer capability, the VSC8123 also has the ability to dynamically modify

its acquisition point in both voltage and phase. This enables the VSC8123 to acquire data in the presence of sig-

nificant symmetry distortion or “bad spots” in the data eye. Integrated voltage and phase adjustment is provided

to offset the sampling point over the entire voltage and phase range of the input data eye. Additional circuitry is

provided to measure relative bit-error rates without affecting the integrity of the active data stream. Using an

external controller, the VSC8123 can acquire frequency, scan the incoming data eye and automatically set its

position to optimize margin in both voltage and phase. This optimization can be one-time on power-up, or set to

continuously repeat without taking the data stream off-line -- no errors will be introduced into the output data

stream as the chip tracks the center of the data eye.

Through the controller interface, the VSC8123 can provide telemetry on the condition of the incoming data

eye and the quality of the acquisition without taking the data off-line, enabling eye profiling, Q-testing, signal

strength measurements, and bit-level error detection/prediction -- all non-invasively.

G52302-0, Rev. 2.0

2/29/00

VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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与VSC8123RB相关器件

型号	品牌	描述	获取价格	数据表
VSC8124	VITESSE	Target Specification	获取价格
VSC8124RE	VITESSE	Support Circuit, 1-Func, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, HEAT SINK, CAVITY DOWN, TQFP	获取价格
VSC8131	VITESSE	2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator	获取价格
VSC8132	VITESSE	2.488Gb/s 1:32 SONET/SDH Demux	获取价格
VSC8132QR	VITESSE	2.488Gb/s 1:32 SONET/SDH Demux	获取价格
VSC8140	VITESSE	2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator	获取价格

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