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VN4012L-GP005 PDF预览

VN4012L-GP005

更新时间: 2024-11-09 01:00:47
品牌 Logo 应用领域
超科 - SUPERTEX /
页数 文件大小 规格书
3页 568K
描述
N-Channel Enhancement-Mode Vertical DMOS FET

VN4012L-GP005 技术参数

生命周期:Transferred包装说明:,
Reach Compliance Code:unknown风险等级:5.62
Base Number Matches:1

VN4012L-GP005 数据手册

 浏览型号VN4012L-GP005的Datasheet PDF文件第2页浏览型号VN4012L-GP005的Datasheet PDF文件第3页 
Supertex inc.  
VN4012  
N-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
Free from secondary breakdown  
Low power drive requirement  
Ease of paralleling  
This enhancement-mode (normally-off) transistor utilizes  
a vertical DMOS structure and Supertex’s well-proven,  
silicon-gate manufacturing process. This combination  
produces a device with the power handling capabilities  
of bipolar transistors and the high input impedance and  
positive temperature coefficient inherent in MOS devices.  
Characteristic of all MOS structures, this device is free  
from thermal runaway and thermally-induced secondary  
breakdown.  
Low CISS and fast switching speeds  
Excellent thermal stability  
Integral source-drain diode  
High input impedance and high gain  
Applications  
Motor controls  
Converters  
Supertex’s vertical DMOS FETs are ideally suited to a  
wide range of switching and amplifying applications where  
very low threshold voltage, high breakdown voltage, high  
input impedance, low input capacitance, and fast switching  
speeds are desired.  
Amplifiers  
Switches  
Power supply circuits  
Drivers (relays, hammers, solenoids, lamps, memories,  
displays, bipolar transistors, etc.)  
Ordering Information  
Product Summary  
RDS(ON)  
(max)  
12Ω  
VGS(TH)  
(max)  
1.8V  
IDSS  
(min)  
Part Number  
Package Option  
Packing  
BVDSS/BVDGS  
VN4012L-G  
TO-92  
1000/Bag  
400V  
150mA  
VN4012L-G P002  
VN4012L-G P003  
VN4012L-G P005  
VN4012L-G P013  
VN4012L-G P014  
Pin Configuration  
TO-92  
2000/Reel  
-G denotes a lead (Pb)-free / RoHS compliant package.  
Contact factory for Wafer / Die availablity.  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
DRAIN  
SOURCE  
Absolute Maximum Ratings  
Parameter  
Value  
GATE  
TO-92  
Drain-to-source voltage  
Drain-to-gate voltage  
BVDSS  
BVDGS  
±20V  
Gate-to-source voltage  
Product Marking  
Operating and storage temperature  
-55OC to +150OC  
Si VN  
4 0 1 2 L  
YYWW  
YY = Year Sealed  
Absolute Maximum Ratings are those values beyond which damage to the device may  
occur. Functional operation under these conditions is not implied. Continuous operation  
of the device at the absolute rating level may affect device reliability. All voltages are  
referenced to device ground.  
WW = Week Sealed  
= “Green” Packaging  
Package may or may not include the following marks: Si or  
Typical Thermal Resistance  
TO-92  
Package  
θja  
TO-92  
132OC/W  
Doc.# DSFP-VN4012  
B082013  
Supertex inc.  
www.supertex.com  

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