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V62/06605-01XE PDF预览

V62/06605-01XE

更新时间： 2024-11-04 11:58:27
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 506K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

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V62/06605-01XE 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-14针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.16
Is Samacsys：N系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：5 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：45000000 Hz
最大I（ol）：0.012 A湿度敏感等级：1
位数：1功能数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.02 mAProp。Delay @ Nom-Sup：18 ns
传播延迟（tpd）：23 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：75 MHz
Base Number Matches：1

V62/06605-01XE 数据手册

 浏览型号V62/06605-01XE的Datasheet PDF文件第2页浏览型号V62/06605-01XE的Datasheet PDF文件第3页浏览型号V62/06605-01XE的Datasheet PDF文件第4页浏览型号V62/06605-01XE的Datasheet PDF文件第5页浏览型号V62/06605-01XE的Datasheet PDF文件第6页浏览型号V62/06605-01XE的Datasheet PDF文件第7页 
SN74LV74A-EP  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
www.ti.com  
SCLS696–JANUARY 2006  
FEATURES  
•
Controlled Baseline  
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
– One Assembly/Test Site, One Fabrication  
Site  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
Extended Temperature Performance of– 55°C  
to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
– 1000-V Charged-Device Model (C101)  
PW PACKAGE  
(TOP VIEW)  
•
•
•
•
•
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
2-V to 5.5-V VCC Operation  
Max tpd of 13 ns at 5 V  
1CLR  
1D  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
2CLR  
2D  
1CLK  
1PRE  
1Q  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
2CLK  
2PRE  
2Q  
•
•
•
Typical VOHV (Output VOH Undershoot)  
>2.3 V at VCC = 3.3 V, TA = 25°C  
1Q  
8
GND  
2Q  
Supports Mixed-Mode Voltage Operation on  
All Ports  
Ioff Supports Partial-Power-Down Mode  
Operation  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the devices when they are powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
LV74AEP  
–55°C to 125°C  
TSSOP – PW  
Reel of 2000  
SN74LV74AMPWREP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
UNLESS OTHERWISE NOTED this document contains ADVANCE  
Copyright © 2006, Texas Instruments Incorporated  
INFORMATION on new products in the sampling or preproduction  
phase of development. Characteristic data and other specifications  
are subject to change without notice.  
1234567...14

中文翻译

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V62/06605-01XE 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV74APWRG4 TI

类似代替

 双路正边沿触发式 D 型触发器 | PW | 14 | -40 to 125
SN74LV74APWR TI

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 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SN74LV74APW TI

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 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

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