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V62/06620-01XE PDF预览

V62/06620-01XE

更新时间: 2024-11-18 12:17:03
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路石英晶振光电二极管输入元件
页数 文件大小 规格书
11页 496K
描述
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

V62/06620-01XE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.23
系列:ACTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:XOR GATE
最大I(ol):0.024 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:14.6 ns传播延迟(tpd):14.6 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
Base Number Matches:1

V62/06620-01XE 数据手册

 浏览型号V62/06620-01XE的Datasheet PDF文件第2页浏览型号V62/06620-01XE的Datasheet PDF文件第3页浏览型号V62/06620-01XE的Datasheet PDF文件第4页浏览型号V62/06620-01XE的Datasheet PDF文件第5页浏览型号V62/06620-01XE的Datasheet PDF文件第6页浏览型号V62/06620-01XE的Datasheet PDF文件第7页 
CD74ACT86-EP  
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE  
www.ti.com  
SCHS357MARCH 2006  
FEATURES  
Controlled Baseline  
SCR-Latchup-Resistant CMOS Process and  
Circuit Design  
– One Assembly/Test Site, One Fabrication  
Site  
Exceeds 2-kV ESD Protection Per  
MIL-STD-883, Method 3015  
Extended Temperature Performance of  
–55°C to 125°C  
D PACKAGE  
(TOP VIEW)  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
Enhanced Product-Change Notification  
4B  
(1)  
Qualification Pedigree  
1Y  
2A  
2B  
2Y  
12 4A  
Inputs Are TTL-Voltage Compatible  
4Y  
3B  
3A  
3Y  
11  
10  
9
Speed of Bipolar F, AS, and S, With  
Significantly Reduced Power Consumption  
Balanced Propagation Delays  
±24-mA Output Drive Current  
– Fanout to 15 F Devices  
GND  
8
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
The CD74ACT86-EP is a quadruple 2-input exclusive-OR gate. This device performs the Boolean function  
Y = A B or Y = AB + AB in positive logic.  
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced  
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the  
output.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–55°C to 125°C  
SOIC – D  
Tape and Reel  
CD74ACT86MDREP  
ACT86MEP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
(EACH GATE)  
INPUTS  
OUTPUT  
Y
A
L
B
L
L
H
H
L
L
H
L
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

V62/06620-01XE 替代型号

型号 品牌 替代类型 描述 数据表
CD74ACT86MDREP TI

类似代替

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SN74ACT86DR TI

类似代替

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SN74ACT86D TI

类似代替

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

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