Datasheet > V61C518256

V61C518256

更新时间： 2024-09-08 22:09:31

品牌	Logo	应用领域
MOSEL		/
页数	文件大小	规格书
12页	61K
描述
32K X 8 HIGH SPEED STATIC RAM

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中文翻译

获取价格

数据手册

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V61C518256 数据手册

PRELIMINARY

V61C518256

MO SEL VITELIC

32K X 8 HIGH SPEED

STATIC RAM

Features

Description

■ High-speed: 10, 12, 15 ns

■ Low Power Dissipation:

– CMOS Standby: 0.5 mA (Max.)

■ Fully static operation

■ All inputs and outputs directly compatible

■ Three state outputs

■ Ultra low data retention current (V = 2V)

The V61C518256 is a 262,144-bit static random

access memory organized as 32,768 words by 8

bits. It is built with MOSEL VITELIC’s high

performance CMOS process. Inputs and three-

state outputs are TTL compatible and allow for

direct interfacing with common system bus

structures.

■ Single 5V ± 10% Power Supply

■ Packages

– 28-pin TSOP (Standard)

– 28-pin 300 mil SOJ

Functional Block Diagram

A₀

A₁

V_CC

GND

Row

Decoder

512 x 512

Memory Array

A₆

A₁₀

A₁₃

A₁₄

I/O₀

Column I/O

Input

Data

Circuit

Column Decoder

I/O₇

A₂

A₅A₁₁A₁₂

Control

Circuit

518256-01

Device Usage Chart

Operating

Temperature

Range

Package Outline

Access Time (ns)

Temperature

Mark

0°C to 70 °C

•

Blank

V61C518256 Rev. 0.3 July 1998

12 3 4 5 6 7...12

中文翻译

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