Datasheet > UT62256CSC-70LL

UT62256CSC-70LL

更新时间： 2024-09-15 22:40:19

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
12页	163K
描述
32K X 8 BIT LOW POWER CMOS SRAM

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UT62256CSC-70LL 数据手册



UTRON

UT62256C

32K X 8 BIT LOW POWER CMOS SRAM

Rev. 1.0

FEATURES

GENERAL DESCRIPTION

ꢀ Access time : 35/70ns (max.)

ꢀ Low power consumption:

Operating : 40/30 mA (typical.)

Standby : 3mA (typical) normal

2uA (typical) L-version

The UT62256C is a 262,144-bit low power

CMOS static random access memory

organized as 32,768 words by 8 bits. It is

fabricated using high performance, high

reliability CMOS technology.

1uA (typical) LL-version

ꢀ Single 5V power supply

The UT62256C is designed for high-speed

ꢀ All inputs and outputs are TTL compatible

ꢀ Fully static operation

and low power application. It is particularly

well suited for battery back-up nonvolatile

memory application.

ꢀ Three state outputs

ꢀ Data retention voltage : 2V (min.)

ꢀ Package : 28-pin 600 mil PDIP

28-pin 330 mil SOP

The UT62256C operates from a single 5V

power supply and all inputs and outputs are

fully TTL compatible

28-pin 8mmx13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

Vcc

A14

A12

A13

A14

A13

A12

MEMORY ARRAY

ROW

A11

512 ROWS × 512 COLUMNS

DECODER

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O1

I/O2

I/O3

Vss

. . .

I/O1

I/O

CONTROL

COLUMN I/O

I/O8

COLUMN DECODER

PDIP/SOP

LOGIC

CONTROL

A10

A11

A10

A11

A2 A1 A0

I/O8

I/O7

PIN DESCRIPTION

A13

Vcc

I/O6

I/O5

I/O4

SYMBOL

DESCRIPTION

A14

A12

Vss

I/O3

I/O2

I/O1

UT62256C

A0 - A14

Address Inputs

I/O1 - I/O8

Data Inputs/Outputs

Chip Enable Input

Write Enable Input

Output Enable Input

V_CC

V_SS

Power Supply

Ground

STSOP

____________________________________________________________________________________________

UTRON TECHNOLOGY INC.

P80027

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882

FAX: 886-3-5777919

12 3 4 5 6 7...12

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