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USB97C102 PDF预览

USB97C102

更新时间： 2024-09-16 03:21:07
品牌 Logo 应用领域
SMSC 控制器
页数 文件大小 规格书
80页 521K
描述
Multi-Endpoint USB Peripheral Controller with Integrated 5 Port HUB

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中文翻译

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USB97C102 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：FQFP, QFP128,.67X.93,20
针数：128Reach Compliance Code：unknown
风险等级：5.92地址总线宽度：20
最大时钟频率：24 MHz最大数据传输速率：12 MBps
外部数据总线宽度：8JESD-30 代码：R-PQFP-G128
JESD-609代码：e0长度：20 mm
湿度敏感等级：3端子数量：128
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装等效代码：QFP128,.67X.93,20封装形状：RECTANGULAR
封装形式：FLATPACK, FINE PITCH峰值回流温度（摄氏度）：220
电源：3.3 V认证状态：Not Qualified
座面最大高度：3.4 mm子类别：Other Microprocessor ICs
最大压摆率：100 mA最大供电电压：3.63 V
最小供电电压：2.97 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches：1

USB97C102 数据手册

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USB97C102  
Multi-Endpoint USB Peripheral Controller with  
Integrated 5 Port HUB  
FEATURES  
!"  
High Performance USB Peripheral Controller  
Engine  
-
-
-
-
Additional USB and ISA Suspend Resume  
Events  
-
-
-
-
-
-
-
-
-
Integrated USB Transceiver  
Serial Interface Engine (SIE)  
8051 Microcontroller (MCU)  
Patented Memory Management Unit (MMU)  
4 Channel 8237 DMA Controller (ISADMA)  
4K Byte On Board USB Packet Buffer  
Quasi-ISA Peripheral Interface  
USB Bus Snooping Capabilities  
GPIOs  
Internal 8MHz Ring Oscillator for Immediate  
Low Power Code Execution  
24, 16, 12, 8, 4, and 2 MHz PLL Taps For on  
the Fly MCU and DMA Clock Switching  
Independent Clock/Power Management for  
SIE, MMU, DMA and MCU  
!"  
!"  
DMA Capability with ISA Memory  
-
-
Four Independent Channels  
Transfer Between Internal and External  
Memory  
Transfer Between I/O and Internal Memory  
External Bus Master Capable  
!"  
!"  
Pin Compatible with SMSC USB97C100  
Complete USB Specification 1.1 Compatibility  
-
-
-
-
-
Isochronous, Bulk, Interrupt, and Control Data  
Independently Configurable per Endpoint  
Dynamic Hardware Allocation of -Packet  
Buffer for Virtual Endpoints  
Multiple Virtual Endpoints (up to 16 TX, 16 RX  
Simultaneously)  
Scatter Gather DMA  
-
-
Four Independent Channels  
Up to 16 Transfers can be Programmed to  
Occur Consecutively Without MCU  
InterventionExternal MCU Memory Interface  
1M Byte Code and Data Storage via 16K  
Windows  
Flash, SRAM, or EPROM  
Downloadable via USB, Serial Port, or ISA  
Peripheral  
-
-
Multiple Alternate Address Filters  
Dynamic Endpoint Buffer Length Allocation (0-  
1280 Byte Packets)  
-
-
-
!"  
!"  
USB Full (12Mbps) and Low Speed Capability  
MMU and SRAM Buffer Allow Buffer Optimization  
and Maximum Utilization of USB Bandwidth  
!"  
Quasi-ISA Interface Allows Interface to New and  
"Legacy" Peripheral Devices  
-
-
-
-
128 Byte Page Size  
10 Pages Maximum per Packet  
32 Deep Receive Packet Queue  
Up to 5 Deep Transmit Packet Queue, per  
Endpoint  
-
-
-
-
-
-
1M ISA Memory Space via 4K MCU Window  
64K ISA I/O Space via 256 Byte MCU Window  
4 External Interrupt Inputs  
4 DMA Channels  
Variable Cycle Timing  
8 Bit Data Path  
-
-
Hardware Generated Packet Header Records  
Each Packet Status Automatically  
Simultaneous Arbitration Between MCU, SIE,  
and ISA DMA Accesses  
!"  
!"  
!"  
!"  
3.3 Volt, Low Power Operation  
5 Volt Tolerant Operation on I/O Signal Pins  
On Board Crystal Driver Circuit  
128 Pin QFP Package  
!"  
Extended Power Management  
Standard 8051 "Stop Clock" Modes  
-
GENERAL DESCRIPTION  
The USB97C102 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple  
endpoint applications. The USB97C102 provides an ISA-like bus interface, which will allow virtually any PC peripheral  
to be placed at the end of a USB connection. Its unique dynamic buffer architecture overcomes the throughput  
disadvantages of existing fixed FIFO buffer schemes allowing maximum utilization of the USB connection’s overall  
bandwidth. This architecture minimizes the integrated microcontroller’s participation in the USB data flow, allowing  
back-to-back packet transfers to block oriented devices. The efficiency of this architecture allows floppy drives to  
coexist with other peripherals such as serial and parallel ports on a single USB link.  
SMSC DS – USB97C102  
Rev. 03/23/2000  
1234567...80

中文翻译

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