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UPD703015AYGC-XXX-8EU

更新时间： 2024-11-07 18:21:15
品牌 Logo 应用领域
日电电子 - NEC 时钟微控制器外围集成电路
页数 文件大小 规格书
48页 327K
描述
Microcontroller, 32-Bit, MROM, 20MHz, MOS, PQFP100, 14 X 14 MM, FINE PITCH, PLASTIC, LQFP-100

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UPD703015AYGC-XXX-8EU 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LFQFP,
针数：100Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.83
具有ADC：YES地址总线宽度：22
位大小：32最大时钟频率：20 MHz
DAC 通道：NODMA 通道：YES
外部数据总线宽度：16JESD-30 代码：S-PQFP-G100
JESD-609代码：e0长度：14 mm
I/O 线路数量：85端子数量：100
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：NO封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not QualifiedROM可编程性：MROM
座面最大高度：1.6 mm速度：20 MHz
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：MOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

UPD703015AYGC-XXX-8EU 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µ
PD703014A, 703014AY, 703015A,  
703015AY, 703017A, 703017AY  
V850/SA1TM  
32-/16-BIT SINGLE-CHIP MICROCONTROLLER  
DESCRIPTION  
The µPD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit single-  
chip microcontrollers that include the CPU core of the V850 FamilyTM, and peripheral functions such as ROM/RAM,  
timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller.  
In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1  
includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,  
all of which are instructions suited to digital servo control applications. As a real-time control system, this device  
provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV  
equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).  
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before  
designing.  
V850/SA1 User’s Manual Hardware:  
U12768E  
U10243E  
V850 FamilyTM User’s Manual Architecture:  
FEATURES  
{ Number of instructions: 74  
{ Interrupts and exception  
External: 8, internal: 23, exception: 1  
{ I/O lines Total: 85  
{ Minimum instruction execution time:  
59 ns (@ 17 MHz operation with main system clock (fXX))  
50 ns (@ 20 MHz operation with main system clock (fXX))  
{ Timer/counters  
30.5 µs (@ 32.768 kHz operation with subsystem clock (fXT))  
16-bit timer: 2 channels  
{ General-purpose registers: 32 bits × 32 registers  
{ Instruction set:  
8-bit timer:  
4 channels  
{ Watch timer: 1 channel  
Signed multiplication, saturation operations, 32-bit  
shift instructions, bit manipulation instructions,  
load/store instructions  
{ Watchdog timer: 1 channel  
{ Serial interface (SIO)  
Asynchronous serial interface (UART)  
{ Memory space:  
Clocked serial interface (CSI)  
I2C bus interface  
16 MB linear address space  
Memory block allocation function: 2 MB per block  
{ External bus interface: 16-bit data bus  
Address bus: Separate output enabled  
{ Internal memory  
(µPD703014AY, 703015AY, 703017AY)  
{ A/D converter: 12 channels  
{ DMA controller: 3 channels  
{ RTP: 8 bits × 1 channel or 4 bits × 2 channels  
{ Power-saving functions: HALT/IDLE/STOP modes  
{ Packages: 100-pin plastic LQFP (14 × 14)  
121-pin plastic FBGA (12 × 12)  
Mask ROM: 64 KB (µPD703014A, 703014AY)  
128 KB (µPD703015A, 703015AY)  
256 KB (µPD703017A, 703017AY)  
RAM: 4 KB  
(µPD703014A, 703014AY, 703015A, 703015AY)  
8 KB (µPD703017A, 703017AY)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. U14526EJ2V0DS00 (2nd edition)  
The mark shows major revised points.  
Date Published September 2000 N CP(K)  
Printed in Japan  
©
2000  
1234567...48

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