Datasheet > UPD464536ALS1-A55

UPD464536ALS1-A55

更新时间： 2024-09-24 23:40:19

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器信息通信管理
页数	文件大小	规格书
28页	285K
描述
x36 Fast Synchronous SRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

UPD464536ALS1-A55 数据手册

浏览型号UPD464536ALS1-A55的Datasheet PDF文件第2页

浏览型号UPD464536ALS1-A55的Datasheet PDF文件第3页

浏览型号UPD464536ALS1-A55的Datasheet PDF文件第4页

浏览型号UPD464536ALS1-A55的Datasheet PDF文件第5页

浏览型号UPD464536ALS1-A55的Datasheet PDF文件第6页

DATA SHEET

MOS INTEGRATED CIRCUIT

PD464518AL, 464536AL

4M-BIT Bi-CMOS SYNCHRONOUS FAST STATIC RAM

256K-WORD BY 18-BIT / 128K-WORD BY 36-BIT

LVTTL INTERFACE/REGISTER-LATCH/LATE WRITE

Description

The µPD464518AL is a 262,144 words by 18 bits, and the µPD464536AL is a 131,072 words by 36 bits

synchronous static RAM fabricated with advanced Bi-CMOS technology using N-channel memory cell.

This technology and unique peripheral circuits make the µPD464518AL and µPD464536AL a high-speed device.

The µPD464518AL and µPD464536AL are suitable for applications which require high-speed, low voltage, high-

density memory and wide bit configuration, such as cache and buffer memory.

These are packaged in a 119-pin plastic BGA (Ball Grid Array).

Features

• Register to latch synchronous operation

• LVTTL 3.3 V Input / Output levels

• Fast clock access time : 5.5 ns / 182 MHz, 6.0 ns / 166 MHz, 7.0 ns / 143 MHz

• Asynchronous output enable control : /G

• Single differential clock inputs

• Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)

• Common I/O using three-state outputs

• Internally self-timed write cycle

• Late write with 1 dead cycle between Read-Write

• Boundary scan (JTAG) IEEE 1149.1 compatible

• Single +3.3 V power supply

• Sleep mode : ZZ(Enables sleep mode, active high)

Ordering Information

Part number

µPD464518ALS1-A55

µPD464518ALS1-A6

µPD464518ALS1-A7

µPD464536ALS1-A55

µPD464536ALS1-A6

µPD464536ALS1-A7

Access time

5.5 ns

Clock frequency

182 MHz

Package

119-pin plastic BGA

6.0 ns

166 MHz

7.0 ns

143 MHz

5.5 ns

182 MHz

6.0 ns

166 MHz

7.0 ns

143 MHz

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M13609EJ4V0DS00 (4th edition)

Date Published January 2001 NS CP(K)

Printed in Japan

The mark • shows major revised points.

1999

12 3 4 5 6 7...28

中文翻译

下载PDF

与UPD464536ALS1-A55相关器件

型号	品牌	获取价格	描述	数据表
UPD464536ALS1-A6	ETC	获取价格	x36 Fast Synchronous SRAM
UPD464536ALS1-A7	ETC	获取价格	x36 Fast Synchronous SRAM
UPD464536LS1-A8	ETC	获取价格	x36 Fast Synchronous SRAM
UPD464618ALS1-A5	ETC	获取价格	x18 Fast Synchronous SRAM
UPD464618ALS1-A6	ETC	获取价格	x18 Fast Synchronous SRAM
UPD464618ALS1-A7	ETC	获取价格	x18 Fast Synchronous SRAM
UPD464636ALS1-A5	ETC	获取价格	x36 Fast Synchronous SRAM
UPD464636ALS1-A6	ETC	获取价格	x36 Fast Synchronous SRAM
UPD464636ALS1-A7	ETC	获取价格	x36 Fast Synchronous SRAM
UPD4664312-B65X	RENESAS	获取价格	STANDARD SRAM