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UPD4701A

更新时间: 2024-11-13 12:24:59
品牌 Logo 应用领域
日电电子 - NEC /
页数 文件大小 规格书
16页 83K
描述
MOS INTEGRATED CIRCUIT

UPD4701A 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD4701A  
INCREMENTAL ENCODER COUNTER  
DESCRIPTION  
The µPD4701A is a counter for an X, Y 2-axis incremental encoder. When a two-phase encoder signal is input  
for the X and Y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel  
form. In addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing  
device such as a mouse or track-ball. The CPU checks the switch input flag or count flag and reads the 12-bit count  
data in two operations, one for the lower byte and one for the upper byte. The key input flag is output together with  
the count data in the upper byte.  
FEATURES  
X, Y 2-axis incremental encoder counter  
Counter input (Schmitt-triggered input)  
X axis: XA, XB 2-phase signal  
4-multiplication count method used  
Y axis: YA, YB 2-phase signal  
Counters: 12-bit binary up/down counters (2 sets, X & Y)  
Reset value: 000H  
Count data output: 8-bit parallel latch output × 2 (including key input flag)  
On-chip 3-contact-point key input buffer circuit  
CMOS  
Single +5 V power supply  
PIN CONFIGURATION (Top View)  
PIN NAMES  
XA, YA : A-phase inputs  
XB, YB : B-phase inputs  
RIGHT  
XA  
XB  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VDD  
D7  
2
RESET X  
YA  
3
D6  
LEFT  
MIDDLE  
CS  
Key inputs  
4
D5  
YB  
: Chip Select  
5
D4  
X/Y  
: X/Y Counter Select  
: Upper/Lower Byte Select  
RESET Y  
RIGHT  
LEFT  
MIDDLE  
SF  
6
D3  
U/L  
7
D2  
D0 to 7 : Data outputs  
8
D1  
CF  
SF  
: Count flag RESET X Counter  
: Count flag RESET Y reset inputs  
9
D0  
10  
11  
12  
CS  
X/Y  
U/L  
CF  
VSS  
Document No. IC-3303 (1st edition)  
(O. D. No. IC-6947A)  
Date Published March 1997 P  
Printed in Japan  
1993  
©

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